13 Feb

New 4DSP White Paper Roundup

4DSP has added a few new white papers to our website to provide more information about some of our products and elaborate on the functional advantages of the technologies and standards they are based upon. We also highlight some of the challenges inherent to several applications and demonstrate how our boards, backplanes and systems can help you achieve a successful design while minimizing both costs and development times.

The product page for our compact and highly adaptable line of FlexVPX 3U VPX-compliant backplanes now features a paper outlining the benefits of this innovative design for VPX systems and some context about the growth of the OpenVPX (VITA 65) standard for systems development. The paper features a contribution from the US Naval Research Laboratory, where the FlexVPX concept was developed as a way to reduce the Size, Weight and Power (SWaP) of embedded systems using two and three-slot backplanes that allow for backplane functionality to be subdivided across several smaller boards. This increases flexibility in the physical packaging of system processing hardware to accommodate the limited physical space available in many military and commercial systems.

 

4DSP VPB601 VPX Backplane

VPB601 VPX backplane

To support our FMCs (FPGA mezzanine cards) that make use of the JESD204B serial interface standard,  another white paper is available on the product pages for the FMC144, FMC142, FMC140, and FMC176 modules. JESD204B offers a reliable, efficient and flexible alternative to the typical LVDS and CMOS interfaces used between FPGA or DSPs and data converters. It reduces the number of interconnects required to interface high-speed (>10 Msps) ADC and DAC converters on an FMC to an FPGA on a carrier card. This makes it possible to design for smaller form factors while maintaining system performance.

 

Typical ADC to FPGA Configurations Using JESD204B (source: Xilinx)

Typical ADC to FPGA Configuration Using JESD204B (source: Xilinx)

 

Cell Tower with Multi-antenna array (photo Gareth Ellner)

Multi-antenna array (photo Gareth Ellner)

We look at the topic of using FPGAs for beamforming in wireless telecommunications and radar applications in the FPGAs for Better Beamforming Performance paper featured on many of the pages for products that are well suited for beamforming, including the Xilinx Virtex-7-based FM788 and the FMC168.

The heavy computational loads and very high bandwidth required to digitally process signals in real time can quickly overtax traditional CPUs and DSPs when used in adaptive beamforming for mobile networks. Much higher performance FPGAs, on the other hand, are ideal for this purpose due to their embedded DSP blocks, parallel processing architecture, and enhanced memory capabilities. FPGAs similarly offer a big advantage over CPU and GPU options in radar systems that employ advanced digital beamforming techniques  because they can reduce, cost, complexity, and power consumption.

 

The VPX for System Development white paper looks at the cost benefits of using the VPX standard (VITA 46) when designing high-performance, rugged embedded systems for aerospace and defense applications involving high-frequency signals. It is available on the product pages for our 3U VPX FPGA carrier cards, such as the VP780, and our VPX systems, including the VPX360.

 

4SDP VPX360

VPX360 Desktop VPX System

The paper outlines the advantages of using designs centered on FPGAs and FMCs to improve project risk management and reduce time-to-market. The OpenVPX ecosystem offers flexibility and performance when planning new designs. It is effective for system upgrades and technology insertion, and it simplifies the incorporation of new technologies such as higher resolution A/Ds and D/As as they become available.

More white papers are in the works on other topics and technologies, so stay tuned!

26 Sep

New White Paper, Video and Improvements for StellarIP

stellar_logo

 

We recently announced some of the numerous updates and improvements that have been made to StellarIP this year to expand its feature set and make it more user-friendly for firmware designers. Today, we direct you to a new white paper that expands on the benefits of our FPGA firmware design tool.

4DSP is constantly working to improve StellarIP to help customers easily implement their designs and quickly get the most out of their hardware. Since its introduction in 2011, a growing number of clients have leveraged the library of proven firmware at the core of StellarIP to more efficiently achieve their design goals. This intuitive tool has also been essential for boosting productivity here at 4DSP, where our engineers have used it to create hundreds of FPGA reference designs for different platforms. These designs have, of course, been passed along to our customers.

Most notable among the improvements made in 2014 are the significant enhancements to the graphical interface, which simplifies editing. Design integrity protection has also been improved to help minimize mistakes and save time. Another key addition is support for Microsoft Windows 8.1, and StellarIP now also has the ability to automatically download updates, which allows 4DSP to deliver the latest features, improvements, and bug fixes directly to users as they become available.

Furthermore, as FPGA industry leader Xilinx prepares to switch to Vivado Design Suite for all of its future FPGA products, 4DSP has added Vivado support to StellarIP. This is important for users because it allows them to regenerate old ISE designs for Vivado for compatible FPGA cards. More improvements are in the works for StellarIP, including plans to streamline the process of firmware updates, add support for VHDL generics, and implement an automated assistant to guide users in the creation of stars (the StellarIP term for IP blocks). Be sure to install the latest version of the tool to ensure that you have timely access to upcoming features.

Selected Updates and Improvements in 2014:

• Improved graphical interface
• Improved library and design integrity protection
• Library merging
• Local library support
• Search in library view to speed up library editing
• More pre-generate checks and better error and warning messages
• Improved log output window (including Xilinx shell outputs redirected to StellarIP)
• File type registration and double-click support from Windows Explorer
• Text file editor
• More custom configuration settings
• Automatic version updates
• Help files
• Xilinx ISE and Vivado support
• Windows 8.1 support

More information, including a new tutorial video, can be found at:

http://www.4dsp.com/software_stellar.php

StellarIP can be used with 4DSP hardware or any third-party FPGA platform under licensing. It is included as part of the Board Support Package (BSP) which is provided for free with the purchase of 4DSP’s FPGA and FMC products.

Please don’t hesitate to contact us if you have additional questions.