FPGA Development Tool - StellarIP
StellarIP simplifies FPGA firmware design by relying on proven IP cores. 4DSP reference designs leverage an extensive library of firmware to ensure that customers are up and running as soon as they receive their hardware. StellarIP is based on a concept where each core is referred to as a star. The stars communicate via wormholes (channels), and a collection of stars is a constellation (top-level entities). StellarIP allows FPGA firmware designers to easily add and connect their application specific code to an existing design. In order to enable maximum performance of FPGA-based hardware, designs created with StellarIP feature ultra-fast PCIe DMA engines, advanced memory controllers, and flexible A/D and D/A interfaces.
StellarIP offers a schematics entry tool to further simplify the design process. Customers can add their own features (Digital Signal Processing core, Interfaces, logic, local memory, etc.) to the reference designs provided as part of 4DSP's Board Support Package (BSP). All 4DSP cores are coded in VHDL, while StellarIP remains language agnostic. StellarIP supports the Xilinx FPGA tools, ISE and Vivado (to be specified at the time of order), and it automatically creates compatible projects. On the host software side, users can easily access the address space for any of the cores present in the design to easily communicate with the hardware.
Xilinx AXI-compliant cores can be easily wrapped into StellarIP stars, allowing them to be reused across different designs. Please refer to the following tutorial on how to wrap an AXI FFT core and use it within StellarIP.
It is also possible to reuse existing StellarIP stars in your own AXI environment. We have created a tutorial that shows how to take the 4DSP FMC110 interface IP and make it an AXI-compliant IP.
StellarIP design flow
StellarIP schematics tool allows easy integration
StellarIP introduction video
StellarIP is not restricted to use on 4DSP hardware. It can be used on any third-party FPGA platform under licensing.