Looking at the Stellar IP blocks for the reference design it seems to be me that if I delete all of the blocks except sip_fmc204 block, I can use that to generate my main code. Is this true?
Not sure what you are trying to do, but in general yes each block can work independently and other customers have done that if theyan AXI system. You still need some sort of master/host interface to send commands that will configure the FMC clock tree and devices.
Also, if this is true does this mean that I just need to sync my data with the DAC#_DACCLKN/P?
Yes you need to be on the clock domain of the DAC to send data out to the DAC, those clock come out of the FPGA. In some DACs those clocks are inputs but here they are outputs so they are generated by the FPGA.
I did have a question on the CLK_TO_FPGA_N/P seems to just be referenced to an external source. If this is true does that mean that my internal clock would be the main sync for data and the DAC clock?
Look at the clocking tree in the FMC204 User Manual. There is a clock chip that sends a clock to the DACs and the FPGA so that all devices get the same clock. The FPGA uses that clock to send data and a clock to the DAC. You have to be in that clock domain when sending data to the DAC.