Hi,
I'm trying to integrate the FMC110 on a v6sx315t FPGA, but I am seeing some placement errors with the clock pins. The adc0 clock uses pin AE33 (fmc_ha_p/n[1]) which is an MRCC pin on the FPGA and it is sent to a multiple of buffers in the serdes_v6 file. See below, where adc0 clock pin is driving CLK_IN_P and CLK_IN_N:
-- Create the clock logic
ibufgds_inst_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IOSTANDARD => "LVDS_25"
)
port map (
I => CLK_IN_P,
IB => CLK_IN_N,
O => clk_in_int
);
-- High Speed BUFIO clock buffer
-- BUFIO replaced by BUFG to reach ISERDES spread over multiple banks in different columns
bufg_inst_clk : BUFG
port map (
I => clk_in_int,
O => clk_in_int_buf
);
-- BUFR generates the slow clock
bufr_inst_clk_div : BUFR
generic map (
SIM_DEVICE => "VIRTEX6",
BUFR_DIVIDE => "4"
)
port map (
I => clk_in_int,
O => clk_div_tmp,
CE => '1',
CLR => CLK_RESET
);
-- Slow clock is driven by a BUFG to equalize delays between fast and slow clock,
-- this is necesary to properly sync/reset ISERDES' spread over multiple banks in different columns
bufg_inst_clk_div : BUFG
port map (
I => clk_div_tmp,
O => clk_div
);
The problem is that the tool places the BUFGCTRL at BUFGCTRL_X0Y28. Since the fmc_ha_p[1] pin is a mrcc pin in clock region x0y1, the tool can't route these (I'm guessing). The following is the error message that I see:
ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
IOB / BUFGCTRL site pair. The clock IOB component <io_fmc_ha_p(1)> is placed at site <AE33>. The corresponding
BUFGCTRL component
<ic_example_top_i/app_inst/fmc_4dsp_wrapper/u_fmc110_top/u_sip_fmc110/fmc110_if_inst/ads5400_phy_inst0/serdes_v6_inst
0/bufg_inst_clk> is placed at site <BUFGCTRL_X0Y28>. The clock IO can use the fast path between the IOB and the Clock
Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest dedicated path to all BUFGCTRL
sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in
its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub
optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
directly in the .ucf file to override this clock rule.
< NET "io_fmc_ha_p(1)" CLOCK_DEDICATED_ROUTE = FALSE; >
Any ideas on solving this? I also tried the "CLOCK_DEDICATED_ROUTE = FALSE" constraint but that gave me a different error.
Thanks,
Billy