Products > FMC103, FMC104, FMC107, FMC108

FMC-104 External Clock Input Signal Restrictions?

<< < (2/2)

arnaudNL:
Dear Sir,


I will close this topic on Monday unless you have something to add.


Best Regards,
Arnaud

norume:
Thanks.  FWIW, I decided to try to avoid the 33% duty cycle issue by replacing the firmware divider with an MMCM block which can produce the required reference at a 50% duty cycle.  This means that the reference clock for the AD9510 PLL on the FMC-104 will be provided by another PLL (inside the MMCM).  I hope this will work at least as well as the hardware approach.

arnaudNL:
Dear Sir,


Thanks, this sounds good. I am happy to see you are able to move forward.


I am closing this topic, feel free to open any new topic if you need that in the future.


Best Regards,
Arnaud

arnaudNL:
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.

Navigation

[0] Message Index

[*] Previous page