Products > FMC103, FMC104, FMC107, FMC108

FMC-104 External Clock Input Signal Restrictions?

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norume:
Can the external clock input be driven with a 117.33 MHz clock at a 33% duty factor (~2.84 ns high, ~5.68 ns low) or does the signal have to have a 50% duty factor for things to work properly?

iklink:
Dear,


The external clock must have ~50% duty cycle. The ADC datasheet defines 40% to 60%, if you would provide such a clock there is a risk that the digitial interface to the FPGA will not work properly.


Best regards,
Ingmar van Klink
4DSP

norume:
I wasn't clear enough with my original question.


I plan to use the external clock input as a reference to the AD9510 PLL -- so the ADCs will still see a 50% clock assuming that the AD9510 can accept the 33% duty cycle reference.  I see nothing on the AD9510 data sheet about restrictions on the reference clock.  Doesn't say that it won't work, but doesn't say that it will, either.


My question was really:
1 - whether or not the FMC-104 circuitry between the front panel connector and the AD9510 would pass the asymmetric signal properly
and
2 - if anyone had experience running the ADC9510 with an asymmetric reference clock.

iklink:

Hello,


Regarding your questions:
1. The external reference goes through some AC-coupling caps and through a balun, I don't expect issues with passing the 33% duty cycle reference, however I wouldn't be surprised if this affects the phase noise performance of the PLL.
2. No we don't have experience with an asymmetric reference clock.


For external reference usage you will have to disable to on-board reference osc. The enable of the on-board oscillator is pulled-up by default and therefore enabled. This enable must be pulled to ground. This enable pin is not directly available on the FMC connector of the FMC104. It is connected to the STATUS output pin of the AD9510.
You will have to program register 0x08 bit [5:2] with value 0000 to pull this signal to ground. Please refer to the AD9510 datasheet and the reference app. It should be enough to change line 210 of FMC10x_clocktree.cpp:


  sipif_writesipreg(bar+0x08, 0x6F); Sleep(10); //charge-pump normal, status Hi-Z = internal ref


to:


  sipif_writesipreg(bar+0x08, 0x43); Sleep(10); //charge-pump normal, status '0' = external ref


Best regards,
Ingmar van Klink
4DSP

arnaudNL:
Dear Sir,


I assume the answer was satisfactory? Please let me know if I can proceed with closing this topic.


Best Regards,
Arnaud

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