Topic: StellarIP_Interface_to_Axi_Interface document  (Read 8407 times)

JoaoFerreira February 03, 2015, 03:48 PM

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Hello


I want to ask if it is possible to follow this guide doing the samething with zedboard and FMC150.
If that is possible, is there something i need to take care when following the guide?


Thanks
Joao

arnaudNL February 04, 2015, 05:39 AM (#1)

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Dear Joao,


This should be all right; some other customers implemented support on other carriers by following this guide.


Best Regards,
Arnaud

JoaoFerreira February 04, 2015, 08:30 AM (#2)

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Ok but basically i can follow this guide and implement the ref design given by 4dsp to fmc150 in vivado.
The only difference here is that the ref design in the guide of fmc110 that is build to be able to configure the clock tree, ADCs and DACs as well as capture data from the ADC and send data to the DAC.
And the FMC 150 ref. design its loading data to DAC and send it to ADC, is that correct?[size=78%] [/size][/size][size=78%] [/size]

arnaudNL February 04, 2015, 08:59 AM (#3)

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Dear Joao,


The AN contains some FMC110 modified support files. You will need to create a set of support files for FMC150, typically you will need to create an xdc file for Vivado as we only have ucfs for ISE.


Note that 4DSP can provide engineering services which go on top of the free reference design provided to our customers. Maybe we could provide you with an AN for your exact hardware combination. You should expect some costs for that. is it a path you are interested by? Shall I get one of our sales engineering in touch with you?


As a firmware engineer it should not be that difficult to look at this AN, the default firmware and implement what you want on top of that, the sky is the limit! Once again many other customers have done that already


Thanks,
Arnaud

JoaoFerreira February 04, 2015, 10:01 AM (#4)

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I'll try to figure out then.


Thanks for the explanation

JoaoFerreira February 05, 2015, 12:51 PM (#5)

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Hi i'm currently trying to understand the Appendix A - LPC pin-out from the FMC150_user_manual.pdf document.


But i'm not understanding the indications given there, i have tried to compare you zedb_fmc150.ucf constraints file, but i can't see any relation between the table from appendix A and the zedboard_master_XDC_REVC_D.xdc.


Because the position in appendix A doesn't match with the LOC number, it is supposed?


Edit: Found the relation



  • « Last Edit: February 05, 2015, 01:12 PM by JoaoFerreira »

arnaudNL February 06, 2015, 05:59 AM (#6)

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Dear Sir,


Good to hear you have been able to find the relation.


Best Regards,
Arnaud

arnaudNL February 06, 2015, 05:59 AM (#7)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.