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fmc161 vivado project

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leongnrl:
Originally I had those loc constraint for sgmii ref clk both p and n pins. However after vivado compiled the design, the location constraint of the p pin of the sgmii_refclk is removed by vivado. You can see that vivado does the same thing to sysclk too. Only either one of the p or n pins of the clocks are remained for the differential clocks. I have looked into the schematic of the implemented design and made sure that the package pin are correctly routed to both p and n pins of the clocks.

lmunoz:
I used the attached constraint file and am I am able to read the CID from the host interface after generating the bit file with Vivado and no other changes.

leongnrl:
Did you just import the ise project to vivado, or create the vivado from scratch and add sources?

May I ask what version of Vivado are you using? I have just tried to compile with my project with your constraint file but I still can't read the CID from host. I am using 2014.3.1. I also got a timing constraint error with your constraint file from clkout1(period 8ns) to clkout2(period 5ns). They are the generated clock from sysclk.

May I ask what is the release data for your 445_vc707_fmc161 too?

leongnrl:
Is it possible that I can get the vivado proj?

lmunoz:

I used StellarIP to generate the Vivado project. I use 2014.2. I also get timing errors but don't have any time to fix it now, probably just missing a constraint not really a design problem.


You can get the built project here:
http://4dsp.com/download/vendor/lfmunoz/vc707_fmc161_forum.zip

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