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fmc161 vivado project
arnaudNL:
Dear Sir,
The only way we can look into that would be to have one of our firmware engineers doing the steps for you. I believe we could get that done in 2-3 man days and obviously this has a cost; I believe nowadays the man days are around 1000$. It might look overkill but we will make sure everything works smooth and the design will be properly tested.
Another option would be to describe what "doesn't work" so I can discuss that with firmware engineers and provide you with some pointers.
Let me know how you want to proceed, I can get you in touch with a sales person if you wish.
Best Regards,
Arnaud
leongnrl:
I will check with my supervisor regarding to money.
So what I did so far was importing the ISE project 445_vc707_fmc161 to vivado 2014.3. All the sources files are imported to vivado except the constraint file. I create a xdc file with all the pinout out without putting any timing constraint yet. Then I use the constraints wizard, which auto detects the clocks, to enter the timing. Afterward I got lots of inter-clock timing error, so I create another asynchronous clock group timing between adc clocks, mac transceiver clock, and sysclk. After that I got timing error for two of the generated clock from sysclk, so I create a false path between the two.
Got the project compile without timing error, program device, run the fmc161app, couldn't obtain sipcid table error. If I program the device with the bit file that I generated from ISE, everything works.
I put debug core to check adc_phy_i_data but the debug core failed to trigger and seems like there is no clock to the debug core. The clock of adc_phy_i_data is adc_phy_i_clk.
Where should I look at now? Any suggestion will be greatly helpful.
lmunoz:
If you are getting a couldn't obtain sipcid table error then the problem is the host interface IP block, so focus on that first. Can you send the xdc file you are using. Converting from ucf to xdc is pretty straightforward for most our designs so if there is an issue with it I will be able to send you the fixed version.
leongnrl:
I am sure that the sipcid table error is not cased by host interface IP blocking since my ISE bit file works fine.
Attached the xdc file.
lmunoz:
I am sure it is working when you build using ISE, but it isn't working when you build in Vivado. If the host interface was working you would be able to read the CID, even if there is no FMC card present. The clocks from the ADCs might not even be running until the FMC is initialized and you can't do that without the host interface working, so there is no point in putting probes in the FMC part of the code until you can at least read the CID.
The most likely cause of your problem is that the transceivers are not working in Vivado, so your host interface is not working. Xilinx recommends regenerating transceivers in Vivado that came from ISE.
In the UCF file there are these constraints:
# SGMII interface to gigabit phy
NET "SGMII_refclk_p_0" LOC = "AH8";
NET "SGMII_refclk_n_0" LOC = "AH7";
NET "SGMII_refclk_p_0" TNM_NET = "gtrefclk";
TIMESPEC "ts_gtrefclk" = PERIOD "gtrefclk" 8 ns HIGH 50 %;
# SGMII interface to gigabit phy
NET "SGMII_TX_P_0" LOC = "AN2" ;
NET "SGMII_TX_N_0" LOC = "AN1" ; #| DIFF_TERM=TRUE;
NET "SGMII_RX_P_0" LOC = "AM8" ; #| DIFF_TERM=TRUE;
NET "SGMII_RX_N_0" LOC = "AM7" ; #| DIFF_TERM=TRUE;
Looking through your XDC file I don't see those. How does Vivado know where to put the transceivers? Look at the built project and see where it placed the transceivers. You might need to add constraints like this
set_property PACKAGE_PIN AH8 [get_ports SGMII_refclk_p_0]
set_property PACKAGE_PIN AH7 [get_ports SGMII_refclk_n_0]
create_clock -period 8 -name gtrefclk [get_ports SGMII_refclk_p_0]
set_property PACKAGE_PIN AN2 [get_ports SGMII_TX_P_0]
set_property PACKAGE_PIN AN1 [get_ports SGMII_TX_N_0]
set_property PACKAGE_PIN AM8 [get_ports SGMII_RX_P_0]
set_property PACKAGE_PIN AM7 [get_ports SGMII_RX_N_0]
If that doesn't work you probably need to LOC the transceivers to the correct location.
# example of a LOC constraint, I'm not sure what the actual location in your design is
set_property LOC GTHE2_CHANNEL_X1Y20 [get_cells sip_sdp_x12_0/gt0_v7_sfpdp_gth_5g0_i/v7_gth_5g0_i/gt0_v7_gth_5g0_i/gthe2_i]
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