You can also decide to only focus on modifying the ISE project created by StellarIP; Modify FMC150 code as well as the top level.
I understand almost everything you said, the only thing that i have doubt is what i quoted above. Correct me if i'm wrong, what you said is that i can generate the ISE project and try to modify it to do what i want, but i need to modify the FMC 150 VHDL code as well?
After some brainstorming, i came to an hypothesis, so since i need to change sip_fmc150 vhdl file to make it connect ADC0 to DAC0, i thought well if i just want to do that and while doing that recording some samples, in a txt file for example, i just need a similar stellar ip star for FMC 150, but without DAC0 and DAC1 wormhole in and ADC1 out wormhole, and insert a DAC0 wormhole out.
So basically i do that out wormholes to process the samples and recording them to a txt file with the help of zedboard connection. And i just have to connect in FMCxAPP the ADC with DAC to make the internal operation of do a bypass from data of ADC to DAC.
In other hand, i'm thinking that this internal bypass is probably needed to program in stellar IP. But that seems strange because i just need to connect the ADC0 wormhole out to DAC0 wormhole in, and i can do this in the reference design given. Of course then in the FMCxAPP how should i input data in ADC? I assume that if i put a sinewave in the ADC input port of FMC150 it is already acquiring data? And probably doing this bypass means that i'll connect ADC to DAC directly and assuming that ADC is acquiring data, it is transmiting data to DAC at the same time.
Thanks for all the help and patience.
Best regards,
Joao