Dear Sir,
As far as the Xilinx error is concerned "Failed to lock the JTAG cable..." you will need to ask Xilinx about that. This is about your Xilinx tools not communicating well with your Zedboard. Unfortunately I cannot do anything about that.
About the hanging PHY negotiation, this could be related to a problem in recent Xilinx tools, you should remove the line with rst text in the download_elf.tcl and see if that helps.
For you own design, well, you have a a reference design delivered as source code, you will need to start by understanding this design and then you will be able to modify it as per your requirement, only a normal integration task.
Best Regards,
Arnaud