Well, I selected Edit->Find->BUFG and checked "Fixed" property for each in Planahead, same for MMCME2_ADV, wrote new .xdc and run implementation in Vivado. New error I get is that BUFG and IDELAY for ads62 are locked to different regions:
[Place 30-719] Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/I] >
sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/iodelay_inst (IDELAYE2.DATAOUT) is locked to IDELAY_X0Y26
and sip_fmc150_0/fmc150_if_inst/ads62p49_phy_inst/bufg_inst (BUFG.I) is locked to BUFGCTRL_X0Y28