Topic: Sampling Frequency for A/D output  (Read 3992 times)

kanzabaig February 04, 2014, 03:01 AM

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Hello,
 
I am trying to analyse the adc0_par signal of the fmc110 core using the chipscope pro tool of Xilinx. I am sampling this signal at 125MHz clock, but the output is not uniform.
We are giving the input sin wave from 1MHz to 60MHz frequency but the output has some jitters in it at irregular intervals.
Kindly tell me the frequency at which adc0_par signal is generated, also the clock synchronized with this signal.

arnaudNL February 04, 2014, 09:11 AM (#1)

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Dear Sir,


The reference firmware will only work as soon the software has ran. We are not using chipscope to see the signal but we get the reference application to save the buffers to file so we can visualize it!


Do you have any problem running the reference design?


Best Regards,
Arnaud

kanzabaig February 06, 2014, 06:57 AM (#2)

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The ref design works fine. My requirement is to take the adc_par data ( the 104 bit data) and store it into a fifo. Kindly suggest me the sampling frequency for adc_par. I need to know the rate at which adc_par is generated.
 
Regards.

arnaudNL February 06, 2014, 09:04 AM (#3)

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Dear Sir,


Can you please be more specific and reformulate your question, I cannot find any adc_par in the firmware source code.


Best Regards,
Arnaud

arnaudNL April 10, 2014, 05:16 AM (#4)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.