Dear 4DSP Support:
I have a system that consists of a FMC104 connected to the FMC-LPC interface of a ZedBoard. I have configured that AD9510 to provide a sampling rate of 100MHz to all four ADC channels with identical frequency and phase. The intent is to sample faster but I started with a 100MHz rate.
My initial FPGA design used a dedicated MMCM for each ADC channel to regenerate a 100MHZ clock and provide proper source synchronous timing at the IDDR elements use to convert the 7-bit DDR bus into a 14-bit SDR bus. I received each ADC channel clock with an IBUFGDS and each DDR data bit with a IBUFDS. A portion of signal processing fr each channel is done in the local channel clock domain and after integration/decimation (factor of 64), FIFOs are used to cross from the local ADC channel clock domain into a common PL fabric clock domain for further signal processing.
The problem with this approach is that MAP complained about the sub-optimal location of the clock I/O pads and the associated MMCM tiles located around the corners of the chip. Since the physical location of the clock inputs is dedicated by the FMC104 design and the implementation of the FMC-LPC on the ZedBoard, I have no control over this. I was able to get around the MAP errors and demote them to warnings by using a "dedicated_route" constraint for each of the four MMMCM clock inputs. However, although I do seem to be getting valid ADC data in SDR format, I am not confident that timing will be robust with further implementations.
I have noticed that the four ADC channel clocks appear to be reasonably well time-aligned and it makes sense to me since the ADS62P49 input clocks are driven by the AD9510 that is configured for identical frequency and phase. Can the clock form one ADC channel be used to supply a single MMCM that could serve for all four ADC channels? This would allow a better placement of the clock pad and MMCM.
If not, are there any other strategies that improve routing if all four MMCMs are used or with fewer MMCMs?
Thank you for your support in advance,
Craig