Yes, by using a bit align machine, the training adjusts the IDELAY relative to the ADC clock. Basically, bit align machine compares the test pattern, finds the 1st and 2nd edges and then sets the IDELAY tap value to the middle. However, this design is optimized for the default frequency that reference design uses. If clock is changed, possibly bit align machine may not set the optimal tap values. You can always change the IDELAY tap values manually instead of using the training. If you open "fmc30rf_afe7225.cpp" in the reference software, you can disable the training and set the manual IDELAY tap values. For more information on IDELAY, please refer Xilinx user guides.
Thanks,
Kyu