Hello,
The reference design produces 500 Msps sinus signal. In the dac IC, it is interpolated to 1 Gsps. My aim was to produce 250 Msps signal in the reference design by simply copying the current sample to the next sample. So the the signal which will be sampled at 500 MHz will look like:
previous case: S0 S1 S2 S3 S4 ...
new case : S0 S0 S2 S2 S4 S4 ....
Normally, this should result in 250 Mhz sampling rate. I hoped to see the same signal in scope but the signal was corrupted. The signal was no more a pure sinus and the amplitude was about 500 mv.
What may be the reason of it? Therotically, i should see the same signal with a lower sampling rate.
Thank you.