Hi Dear Kyu,
Sorry for not having expressing the question well.
1. Explanation to question 4: First I’d like you to look at Figure 11 in the FMC116_FMC112_user_mannual. There are three ports: SCLK, N_CS, SDIO which are connected to CPLD and we can program the device through these three ports, which are also connected to CTRL(0), CTRL(1) and CTRL(2) on the FMC connector. Then I’d like you to look at Figure 12, which shows how to write some data into a register. You can see that N_CS is “0” for 24 cycles of SCLK. I just want to say that, N_CS is “0” for only 24 cycles in this case, right? It cannot be “0” for 48 cycles to write TWO registers, can it? We can only write one register a time, can’t we? If so, there must be some SCLK cycles between two sequential writing operations during which N_CS is “1”, right? I just want to know how many cycles there has to be between every two operations.
2. I am still not clear about the trigger signal and clock signal. According to your answer, Trigger tells the ADC to capture the data. Then it is the trigger signal which decides the sampling frequency rather than the clock signal, isn't it? Then what is clock signal used for? Are there any constraints or relations between the frequency of trigger signal and that of clock signal?
Xun