Arnaud, I have not seen the issue running the reference bitfile that you provide. But I am using the core hardware blocks from your reference design and have added them to a larger project. The steps that I take to initialize the board are the same as yours, except for pin alignment. I am aligning the bits by enabling the ramp test pattern in the ADC and advancing the iodelays until the pattern arrives as expected. I have come across certain scenarios where after resetting the clock buffer and the iserdes block, scanning through all 64 delay taps does not align the data. If that happens, I reset the clock buffer and iserdes block again and try the taps again. I repeat this process until finally the iserdes block initializes to a proper state where I can adjust the tap delays until data is properly aligned. I don't know what the bitslip is supposed to do that is why I am asking if the bitslip affects the way the iserdes deserializes the data.
The other problem is that this reset issue that I've described above seems to be happening with different builds of my firmware, which could mean it's affected by the routing during implementation.