FPGA Development Tool (Stellar IP)

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The 4DSP board support package includes the Stellar IP software tools to design an FPGA firmware onto the 4DSP hardware.

4DSP has developed Stellar IP to simplify the creation of firmware design on an FPGA. Stellar IP assists and simplifies design by using a proven IP core (block with a specific function) that is safely reused (because of a standard interface and uniform design) and is usable on different platforms (such as Altera and Xilinx).

Stellar IP splits the algorithm into blocks, called Stars. Stars have a generic pinout to allow modularity. A Constellation defines a library of Stars and Worm Holes (common-protocol connections between Stars).

The Constellation is described in the Stellar IP Description File (SDF) which uses an XML structure. The SDF is used by Stellar IP to create a VHDL design file that initializes all the Stars and automatically assigns address ranges for Stars that require settings to make sure the Worm Holes are correct.

Furthermore, Stellar IP will create the configuration file for the FPGA device and setup simulations. Simulation of the constellation is further simplified when the Stars are designed with the 4DSP command interface which will allow sending and receiving of data and commands from a script file without the need to code a single line of VHDL.

The following image depicts an example constellation that implements 4 stars that are interconnected using wormholes.

Stellar IP allows the design engineers to:

• generate a top-level VHDL file based on a description provided by the user and compatible with the FM48x line of products
• start the FPGA compilation tool (ISE) and generate a .hex file that can be used on the 4DSP line of products
• simplify the integration of a new functionality in an FPGA design written in any description language commonly compiled by the synthesis tool (VHDL and Verilog)
• have a library of off-the-shelf IP cores that can be easily integrated in an FPGA design
• shorten integration time by relying on well-tested IP blocks

Stellar IP is not restricted to use on 4DSP hardware. It can be used on any third party FPGA platform under licensing.