sFPDP core
4DSP's serial front panel data port core for FPGA is based on the ANSI/VITA 17.1-2003 standard. This intellectual property core can be implemented on any Xilinx FPGA families.
Specifications
- Up to 2.5Gbps (using MGTs)
- Up to 230MBytes/s per optical transceiver
- Unidirectional and bi-directional links
- Framing supported: dataflow control, PIO per specification, copy mode, copy-loop mode and CRC
- Fully compliant ANSI/VITA 17.1-2003 SFPDP standard
Target devices
- Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5
Purchase this core or request more information by sending an email to sales@4dsp.com.
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