JPEG compression core
4DSP's JPEG compression algorithm for FPGA is based on the ISO/IEC 10918-1 standard. This intellectual property core can be implemented on the Xilinx Spartan 3, Virtex-II, and Virtex-4 FPGA families. Data is fed to the FPGA through a user selected interface and is compressed into a JPEG JFIF format.
Specifications
- Up to 500 frames/s
- Up to 2048 x 2048 images
- Up to 16-bit pixel resolution
Enlarge original picture | Enlarge compressed picture
JPEG algorithm
The core compresses data by leveraging configurable tables, i.e. quantization and Huffman tables and can be customized to meet end users' architecture specifications. The compression ratio, depending on the quantization and Huffman tables, can vary from 0 to 100.
Target devices
- Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3
Purchase this core or request more information by sending an email to sales@4dsp.com.
Downloads
Docs
JPEG_core_specifications
(42kb)
JPEG2000_Analysis (307kb)
Compression_core_overview (137kb)
