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JPEG Compression Core

Description

4DSP's JPEG compression algorithm for FPGA is based on the ISO/IEC 10918-1 standard. This intellectual property core can be implemented on the Xilinx Spartan 3, Virtex-II, and Virtex-4 FPGA families. Data is fed to the FPGA through a user selected interface and is compressed into a JPEG JFIF format.

Specifications

• Up to 500 frames/s
• Up to 2048 x 2048 images
• Up to 16-bit pixel resolution

Enlarge original picture | Enlarge compressed picture

JPEG algorithm

The core compresses data by leveraging configurable tables, i.e. quantizations and Huffman tables and can be customized to meet end users' architecture specifications. The compression ratio, depending on the quantizations and Huffman tables, can vary from 0 to 100.

Enlarge Diagram

Target Devices

• Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Virtex-6, Spartan-3, Spartan-6

Stellar IP available for this product. A simple way to design FPGA firmware with automated code and bitstream generation

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Ordering Information

Purchase this core or request more information by sending an email to sales@4dsp.com.

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