4DSP Support Forum

Products => FMC Products => Topic started by: dduque on November 03, 2014, 01:41 PM

Title: FMC160 VHDL bug
Post by: dduque on November 03, 2014, 01:41 PM

      We've found a bug in the VHDL code for the FMC160 and wanted to advertise it to anybody using this design.  In the file fmc160_ctrl.vhd, pulse retimers are used to transfer momentary pulses from the MAC clock domain (clk_cmd) into any unrelated domain which must respond to that pulse.  In the case of the Waveform memory, the "LOAD" control bit is used to reset the address counters in preparation for a DMA push.  Since the DMA push takes place in the MAC clock domain to begin with, there is no need to retime the pulse.  In the VHDL, however, the pulse gets retimed to the DAC clock domain before being used.  In general this will not cause a malfunction as long as the DAC clock (1/16th of the sample rate) is slower than the MAC clock (125 MHz).  And indeed with the default settings in Fmc160APP.exe, the DAC clock is 1.8Gsps/16 = 112.5 MHz < 125 MHz.  When I increased the sample rate to 2.4 Gsps, however, the resulting DAC clock is 150 MHz > 125 MHz and as a result, the retimed LOAD pulse is too brief to reliably reset the DPRAM address counters in the clk_cmd domain.  The symptom of this is waveforms which some times are not fully updated following a DMA push.  By removing the pulse retimer, the counters are always reliably reset and waveforms are always completely updated.  Feel free to contact me with any questions.

Alex Duque
Title: Re: FMC160 VHDL bug
Post by: arnaudNL on November 04, 2014, 07:34 AM
Dear Alex,

This is very valuable feedback, thanks for that! I am forwarding that to the firmware design team.

Best Regards,
Title: Re: FMC160 VHDL bug
Post by: arnaudNL on November 11, 2014, 07:55 AM
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.