4DSP Support Forum

Products => FMC Products => FMC122, FMC125, FMC126 => Topic started by: jchang on May 06, 2013, 01:30 PM

Title: FMC125 Unconstrained path analysis - Hold paths
Post by: jchang on May 06, 2013, 01:30 PM

I looked at the Post-Place & Route Static Timing report generated by ISE, and there are many paths under "Unconstrained path analysis - Hold paths" that are listed as failing.  It's not clear to me if these failing paths could cause problems, but it is concerning.  Shouldn't these paths be constrained?

Title: Re: FMC125 Unconstrained path analysis - Hold paths
Post by: arnaudNL on May 07, 2013, 06:28 AM

Dear Sir,
Our designers place the required constraints generally. No action required I assume, first run the design and see if that works.
You can provide me with a list of unconstrained nets, we can look at it quickly but I am not too concerned about that.
Best Regards,
Arnaud

Title: Re: FMC125 Unconstrained path analysis - Hold paths
Post by: jchang on May 07, 2013, 10:48 AM

Here's the section of the timing report that lists the hold errors.

Title: Re: FMC125 Unconstrained path analysis - Hold paths
Post by: ebarhorst on May 07, 2013, 12:22 PM

Hi


the report shows these are all cross clock domain paths. These are taken care of by design and do not require constraints.


Best regards,
Erik

Title: Re: FMC125 Unconstrained path analysis - Hold paths
Post by: jchang on May 07, 2013, 01:44 PM

That's good to know.  I think some timing ignores for these specific paths would be useful for indicating the intent that these paths are taken care of by design and getting rid of the hold errors in the timing report.