Port B/C/D are located in clock regions above/below each other, but port A is not. This means that the data for port A cannot cross into a common clock domain through the ev8aq160_phy_fifo since none of the other clock domains are adjacent to it (since multi-region clocking using a BUFMR+BUFR only clocks to the the clock region of the BUFR and the ones above and below). Is the above correct? If so, is there a solution to this and/or is a FMC700 required? |