4DSP Support Forum
Products => FMC Products => FMC150 => Topic started by: paulleons on May 15, 2014, 02:26 PM
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Hello,
I am trying the reference design provided with ML605 and FMC 151. I am generating a 5MHz sine wave with an amplitude of 1V. I am communicating with the board with Ethernet. I am using the following cable to connect the FMC 151 (MMCX) with a signal generator : http://www.pasternack.com/mmcx-plug-bnc-female-rg174au-cable-assembly-pe36738-48-p.aspx
The waveform obtained with noise is attached with this post. I was wondering if the board would have so much noise in the waveform. I also noticed that the board is becoming much warmer IC. Is this normal?
regards,
Paul
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Hello Paul,
Could you provide me with the serial number of your FMC151 and could you let me know what kind of firmware and software you are using in your setup? Are you using the bitsteam from 4DSP and the GUI from 4DSP?
Thanks in advance,
Peter
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Hi,
Thanks for the reply. The part no of the kit is FMC151-2-1-1-1 and serial no given was 0018 with PBC #KDJV000018. Firmware downloaded was for the reference design (418_ml605_fmc151). I used FMC analyzer to generate and observe data. I noted that DAC is working perfectly fine as it creates a sine wave without any noise. For ADC, when the frequency is changed, the wave appears to be a sine wave but has too much noise.
Help would be greatly appreciated.
Thanks & regards,
Paul
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Are you using the loopback cable to connect the DAC0 to ADC0? Or are you generating the signal externally?
Also, can you run the reference application (FMC15xApp) and look at/or attach the resulting *.txt file to the forum?
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Hello,
I tweaked the reference design to generate analog values through DAC. I also modified the design to sample analog signal at 100 MHz and send these values to DAC.
If a square wave is given as an input from a function generator, a square wave is observed at the output, but with a lot of noise again (picture name : square_wave2ADC(1).tif).
I went back to reference design provided by 4DSP and downloaded the firmware (available at.../4Dsp/Common/Firmware/Recovery/418_ml605_fmc151 directory) for ML605 board. The connection was made from DAC0 to ADC0. Signal is generated from the DAC using the FMC analyzer software. A sine wave was generated without any problem and was observed on the oscilloscope (picture name : qfile_01.tif).
But when the values are observed in the host computer using the FMC analyzer tool the waveform that's observed looks totally absurd (picture name : test_adc.jpg and text file : test_adc_1.txt ). This makes me wonder if the ADC is really working or not. How can I make sure that the ADC is working?
Any help/suggestion would be very helpful. Thank you.
regards,
Paul
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To verify if the board is working or not, can you please run our DEFAULT (given) firmware with NO modifications with the REFERENCE software (not analyzer, but the Fmc15xApp.exe or you can build it from the source)?
Hook up a loopback cable from tx to rx and let us see the results on the txt files for both tx and rx.
Thanks.
Tony
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Thank you for the reply.
By reference design without any modifications you mean the firmware available at the following directory right.
.../4Dsp/Common/Firmware/Recovery/418_ml605_fmc151 directory
I downloaded this firmware in my all the previous discussions.
I am having trouble in running the Fmc15xApp.exe reference software. I use windows 7, and when I double click this exe file (in.../4dsp/FMC Board Support Package/ Bins/Fmc15App.exe), it opens and closes immediately.
When you refer to the .txt file, do you refer to the text file that can be generated by analyzer software?
Thanks again.
regards,
Paul
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Hi,
You'll need to open a command prompt and execute in the command line:
Fmc150App.exe 1 ML605 device_index 0
where device_index is where your ethernet port device is (similar to the Analyzer value).
You should get a bunch of txt files for the generated tx function (software value sent on DAC) and the corresponding result should show up as adc files.
On the firmware - yes, use the default bit stream.
Tony
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Thanks a lot for the reply.
I ran the application which created 4 text files.
These files are attached with the document. Please observe these values and let me know how to proceed.
Thank you.
regards,
Paul
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Hi paul,
It definitely looks like there is something wrong with the hw or firmware. But just to double check, what version is your BSP? (there should be a date on the 4FM GUI application for the version).
And just to verify, your cable is just a standard loopback cable (short, without any filters or anything in between, right?)
I will ask one of our guys to start the process to return the board.
Tony
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Hi,
The 4DSP version installed on the host computer is 2.230.1 released on 9 May 2014. There is no filter connected to the loopback system.
Please note that I connected DAC0 to ADC 0. I used the 2 of the following cables to create a loop-back design.
http://www.pasternack.com/mmcx-plug-bnc-female-rg174au-cable-assembly-pe36738-48-p.aspx
Please let me know how to proceed further.
regards,
Paul
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Hi Paul,
Just one more try - attached is an exe file with the later build of the BSP for the 15xAPP. please attach the adc files again with this run.
Tony
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Hi,
I replaced the FMC15xApp.exe with the new exe file that you gave me. When I run, I get the following error :
The program can't start because of missing MSVCR110D.dll is missing from your computer. Try reinstalling the program to fix this problem.
I am downloading the latest available BSP from 4DSP and I will run the FMC 15xApp available in the latest version.
I would like to know if the firmware in the RECOVERY directory would change depending on the BSP updates?
regards,
Paul
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Yes, the firmware can be changed if there were issues found and fixed/addressed. You should enable extraction of firmware when you update the BSP and use the latest one.
I ran the latest software (BSP release as of last Friday) on a board that is under testing in our lab and the ADC results looks good. I think I gave you the one which was built under debug mode (sorry). If you download the latest BSP it will have the right build.
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Hello,
I updated by BSP to latest version (one released on last friday), but problem still persists. I have uploaded the latest set of text file after running FMC15xApp.exe.
Paul
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Hello,
I ran the same test, this time connecting to channel 1 instead of channel 2 and I get much better results. The text files are uploaded. But still, in the analyzer, I still see lots of noise.
Please suggest a solution for this problem.
When I see the adc1.txt files, I see values from -31,000 to 32,000. With a 14 bit ADC, I expect values from 0 to 16383 or from -8192 to 8191. How is it possible to interpret the values
Thank you.
regards,
Paul
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The values are 16 bit aligned, so this is normal that you'll see the results up to +/- 32k.
However, the signal looks clipped (i.e. overpowered). Usually when it's overpowered, you get that type of waveform where the harmonics are completely overpowered.
Also, how high is the temperature on the ADC board? I assume there is a fan or some cooling on the ADC board? It gets really really hot and it could be damaging to the board if there is no cooling.
Can you build the reference application with Visual Studio? Our firmware/hardware engineers suspect perhaps a timing issue on that particular board (timing adjustment might be needed).
You can also feed an external signal in but making sure it won't over clip the ADC and see if the result change. Please only use the reference application when you do this type of data capture.
If you can tweak the reference application, you can change this:
2. If they are setup they can tweak the tapiod_clk value in main.cpp. The range is from 0 to 31 case CONSTELLATION_ID_FMC151_ML605: printf("Found ML605 hardware\n\n"); tapiod_clk = 0x00; tapiod_data = 0x00; break;
the range for tapiod_clk is from 0 to 31. if you can't change it perhaps I can build you binaries that has differnet values (5, 10, 15, 20) to try out.
Tony
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Hello,
Yes. The temperature of the board is a high. We don't have any cooling mechanism and the board do not have any cooling system either.
It would be great if you could build the binaries after building the reference application so that I can test it. We are already occupied with the design part of the project and we are loosing too much time because of the problems in the board.
If there is a timing issue with this board, I could check everything with a spare ML605 board and see if I have any problem. When I give external signal, how do I make sure that the signal does not get clipped by the ADC?
Our deadline for deliverables are approaching and hence I would like to know if we can get a new board shipped to us. Once we get the new board, we can ship-out the old board.This will enable us to work atleast with the channel 1 of the ADC.
Paul
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I would start the generator with -3 dBm power and slowly go up. You should not see data near 32k or -32k at that point.
The harmonics that I see from your latest output shows that the signal seems to be clipped. Also, I assume you look at the generator waveform, right?
On the software - you guys do not build the C code at all? How do you test your own design? I can provide the binaries but at some point you will need to build the code.
Anyway, I will send you a few RAR files of various settings shortly of the executable.
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On cooling - you must have fan blowing on the FMC151 card or another air cooled mechanism. If not, the board could be damage and you can definitely see problems that you're currently experiencing. You can use a desktop fan for this if you don't have the other types. Basically it has to be air cooled.
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Attached are two RAR files - tap delay 5 and tap delay 10. Please run it in command prompt in administrator mode and let me know if it works or not.
You will need to run this file on a computer that has the BSP installed (so the appropriate DLLs are in the path).
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Also, what revision of ML605 do you have? we tested them with rev D but there are later boards that can potentially affect timing on the lines - you'll really need to get the code and compile and change the tapiod_clk values in order to adjust the timing differences on the board.
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Hello,
I have uploaded the text files for both the tap delays in two posts.
We do not use the software provided by 4DSP much. We use the software just to make sure that the board is working as expected. We added our own hardware units to get the ADC values and do some processing. Values are also generated by our module to the DAC.
We are using a desktop fan for cooling now. I think we are using an older version of the board as it was purchased at least 1-2 years back. The FPGA used inside is XC6VLX240T-1FFG1156.
Paul
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A Second set of text files is uploaded:
Please note that the DAC is connected to ADC0.
regards,
Paul
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Paul,
The thing is, in order to rule out the hardware/firmware issue, we need to run with a predetermined set of known firmware and software. Namely, our reference software and default firmware. Your issue looks similar to basically timing related problems on the clock. In our reference software, you can adjust it here in main.cpp:
case CONSTELLATION_ID_ML605:
case CONSTELLATION_ID_FMC151_ML605:
printf("Found ML605 hardware\n\n");
tapiod_clk = 00; tapiod_data = 0x00;
break;
Our hardware/firmware engineers feel that if you return the board, it'll still pass the test we run verifying that te hardware is fine. The issue with the signal is that we see bit flips (i.e. timing of ADC data coming in to the FPGA). It's important that the boards (ML605) have similar revisions because some of them will have longer or shorter trace lines from the FMC to the FPGA, that will affect timing delays.
Can you compile the reference software with the reference firmware and try out a few values on tapiod_clk?
Tony
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Hi,
The second set is out of range for sure (delay of 10) - i don't see the ADC0 for the first set (delay of 5) only ADC1.
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Sorry,
I will attach all of delay 5 again.
regards,
Paul
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Hi Paul,
Are you using the loopback cable (DAC to ADC directly with our default firmware) without an external generator? You'll need to do that for these tests in order to make sense. The second set (delay 10) looks like there is a squarewave inserted).
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Actually, both of these sets look like ADC0 has a squarewave. Are you sure you're looping it back directly???
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Sorry.
I forgot to do a loop-back and I was monitoring how a square wave would look after the ADC conversion.
I am uploading the loop-back files in these post.
Paul
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Second set of text files :
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Hi Paul,
Thanks for the correction.
Here are two more sets of delays (27 and 22). Basically the default app has 0 delays and I am trying to figure out if going forward 5 to 10 or back wards -5 to -10 change the received.
Please let me know which set corresponds with which delay, it'll help the process.
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Hello,
Please find the text files for tap 22:
Also, note that I changed to a new ML605 board, but of the same type and version .
Paul
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Please find the text files for tap 27:
Paul
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Hi Paul,
Attached is the log file that i see when I run the application - you should see the SAME settings (voltage and frequencies) - please verify that this is what you see using the provided application (in the c:\program files\) as well as what i gave you (the list of delays).
I tried the application with the firmware and at tap delay 0, and tap delay 10. As you can see, tap delay 10 is bad, but tap delay of 0 is good (the default value).
I'll try to get an applicatio nto you that will create 31 differnet cases in a long loop that will try each tap delay. You can use Visual Analog as well to verify the results. IDEALLY though you guy sshould be doing this and setting the tap delays because it's dependent on the board that you're using (trace length, etc. will affect it).
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Here is the log file. Please verify this is the same as what you see on your screen.
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Yes.
Log files are identical except that the number of devices is 6 in my log file instead of 3 and the temperature is 29 instead of 39.
Paul
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Hi John,
Attached is a new binary file - this one will go through all 32 available tap delays (0 to 31) and save adc0 and adc1 into 32 different txt files. Please RAR the resulting files with the loopback after you're done.
This allows us to see if there is any value that will result in correct signal.
Tony
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After the run, you should see:
adc0_tapioclk_0.txt to adc0_tapioclk_31.txt files
then the same for adc1. Go ahead and RAR or zip up all the files and I can take a look. The delay range can be narrow apparently.
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Hello,
I have uploaded the zip file which has all the 32 files.
Paul
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Paul
can you check file #26? I believe that delay looks good on your board.
I'll need to check with our firmware guys to see what's going on.
Tony
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Hi,
Attached is the Fmc15x for tap delay 26. You should get decent results now with this on your current hardware setup.
Peter will probably get back with you on the resolution for this issue in the long run. In your code you'll need to account for the delay - our reference code for your current platform will need to change to:
case CONSTELLATION_ID_ML605:
case CONSTELLATION_ID_FMC151_ML605:
printf("Found ML605 hardware\n\n");
tapiod_clk = 26; tapiod_data = 0x00;
break;
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Hello,
So I guess, I will run this .exe file and then I download my custom design (which has some added modules for the reference design) and continue with my work.
So now, the values that I observe in chipscope is assumed to be correct. Right?
regards,
Paul
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Well, you will need to tune your design to the right delays.
basically, the lines coming in from the ADC going into the FPGA - there is a clock and the signals. The delay adjust the clock so that it syncs up with the bits coming from the ADC. If it's not synchronized, then you'll see the issue. I'm just making sure the hardware doesn't have problems - there could be issues in your design that can result in the signal that you have sent me earlier (as well as in our refernece deisgn which may be addressed since the leeway is a bit tight).
In our design, the software tune the delay by writnig a value to the FPGA and the FPGA adjust the delay of the ADC signals coming in. Your design may be different.
Go ahead and give the app with delay of 26 a try and with our default reference firmware and your current hardware setup, you should see good signals in loopback. Then you can use a signal generator and should see decent results.
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Thank you.
But is it possible to slow down the clock directly in the ISE project (which is created by Steller IP with no modifications of default design from 4DSP for ML605) so as to synchronize the clock with the data.
regards,
Paul
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While it's possible to add delays to the firmware, you'll have to recompile it several times to get the right timing iwth hardware, right? That's a significant amount of time to spend on it.
Our reference design utilizes software and firmware so that certain things such as delays in the line which may vary amongst different hardware platforms and configurations can be done directly in software without having to recompile firmware.
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Hi,
I am a collaborator working with Paul on this design. I think it might help to provide some context for this problem.
We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.
We modified the reference VHDL, but during synthesis in ISE, we are having difficulty meeting timing. So, there are two issues:
1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?
Thanks!
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Please open a new topic on this. As far as the tap delay, please see the previous posts. It is designed to sync the lines of the clock and the adc traces to the FPGA's logic.
Hi,
I am a collaborator working with Paul on this design. I think it might help to provide some context for this problem.
We are trying to generate a 500 Hz square wave from the DAC, and integrate over part of the response from a circuit. The generation seems to work seamlessly. The integration should be done over 50K samples from the ADC, 0.1 ms after the positive edge, for each period of the generated signal.
We modified the reference VHDL, but during synthesis in ISE, we are having difficulty meeting timing. So, there are two issues:
1. Which signal(s) should we extract from the given design to get the ADC outputs?
2. What tap delay should we use, and how should we insert it directly in the VHDL logic?
Thanks!
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Hello,
Is there a way to fix these problems by slowing down the sampling frequency, let say from 247 MSPS to 10 MSPS.
My application does not require very high sampling rate and hence, I could still work with a slower frequency if that could fix the problem.
Paul
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Paul,
it does not matter what frequency you use, etc. This is an inherent issue with any firmware design. You have an external part that a FPGA is trying to interface - the FPGA compiles and generate a bit file - and can generate different routes depending on how much has chagned, right? Those routes changes the delay of the lines to the FPGA. It's an inherent issue in any FPGA design when interfacing with an external device. We provide a way to be able to program it with software with the firmware to tune the delay. There is plan to do it automatically in firmware in the future.
Anyways, from what we have done, the hardware of your FMC151 is working, it's just the tap delays needed to change from the default value in software. If you need to change the frequency, you'll need to look at the ADC configuration in software and you'll need to build the software yourself.
We can support you on using our reference software and reference firmware but beyond that you'll need to contact sales@4dsp.com.
Tony
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Thanks for the reply.
But I have some more concerns regarding the tap-delay. I have my own custom Ip which connects to two signals, namely phy_out_data0 and phy_out_data1 (from the reference design) and I observe these values in chipscope.
The was implemented and had met timing. Now, a tap-delay of 0 was observed to be ideal as I got a sine wave similar to untitled.jpg.
However, when I see the same waveform in chipscope, the sine wave seems to be distorted as in image_0.jpg and image_1.jpg.
Is there a possible explanation for this behavior?
Paul
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Paul,
I would double check the chipscope sampling clock then.
The fact you get proper data saved to file indicate the reference design is working. Modification on the reference firmware are not supported unless you have a extended technical support contract in place.
Because you indicate you have the proper data saved to file indicate the initial issue is resolved and therefor I am closing this topic.
Best Regards,
Arnaud
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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.