4DSP Support Forum

Products => FMC Products => FMC30RF => Topic started by: kcfarleyswmacb on October 16, 2013, 11:19 AM

Title: FMC30RF FIFO SAMPLE SWAP
Post by: kcfarleyswmacb on October 16, 2013, 11:19 AM

4DSP Support:
 
  afe7225_fifl.vhd line 136 of sip_fmc30rf.vhd. There is a comment that says - Undo sample swap by FIFO. Please explain and elaborate. Where and why was this done? Do the samples need to be swapped on TX side also?

Title: Re: FMC30RF FIFO SAMPLE SWAP
Post by: Kyu on October 16, 2013, 11:59 AM

This is for rearranging the sample order. AFE7225_STORAGE_FIFO has a 32bit input and a 64bit output. The read out data from the FIFO has the first sample at bit[63:32] and second sample at bit[31:0]. Thus, sample order is rearranged by swapping the samples. At TX side, FIFO has a 64bit input and 64bit output so the swapping is not required. Please refer to the Xilinx FIFO user manual for more details.


Thanks,
Kyu

Title: Re: FMC30RF FIFO SAMPLE SWAP
Post by: kcfarleyswmacb on October 16, 2013, 12:38 PM

Kyu:
 
    With 12 bit I/Q expanded to 2*16 = 32 bit. Why do samples need to be put into 64 bits[32 bit to 64 bit Fifo]?

Title: Re: FMC30RF FIFO SAMPLE SWAP
Post by: Kyu on October 16, 2013, 01:56 PM

It's because StellarIP interface uses 64bit data bus. For this case, 2 samples are read through the StellarIP interface at each time.


Thanks,
Kyu