4DSP Support Forum
Products => FMC Products => FMC150 => Topic started by: varunv123 on June 12, 2013, 06:55 PM
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Hey
I set up the FMC150 with the Xilink KC705 board using the quick set-up guide and get a sine waveform on the oscilloscope as expected. I would now like to be able to generate a random wavefrom of my choice (for example another sine wave of a particular frequency or a OFDM waveform). I presume this would be done by inputting data of my choosing into the DAC as apposed to the data that is inputted by default which makes the sine wave. Do you know how I would go about doing this?
Thanks for your help!
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Dear Sir,
FMC150App is indeed creating buffers on the fly, check at GenerateWaveform16() in main.cpp. The software source code is installed under 'C:\Program Files (x86)\4dsp\FMC Board Support Package\Refs\Software\FMC150'
Best Regards,
Arnaud
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Thanks Arnuad.
What would be the best way to modify the generatewaveform16() function to create a waveform of my choice? Can I just open the FMC150app.vcxproj file in visual studio, modify the code to how I want, compile it and then call the FMC150app.exe function the same way its called in the quick start guide? If you could give me a rough outline on how to proceed that would be great!
Thanks again for your help
Best
Varun
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bump
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Dear Varun,
Correct, you can modify the software and recompile it. Then you execute it the same was as the initial software.
This is about browsing a project file in Visual Studio 2012 (Express or PRO) and build the project.
Best Regards,
Arnaud
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Dear Arnaud,
Thanks for your help, I was able to load whatever samples I wanted by modifying the project. For the last few days I've been looking to try to constantly stream samples into the DAC, and from the ADC, as apposed to now where, as far as I understand it, the program loads bursts of 65536 samples onto the FPGA and then the firmware on it cycles through these samples indefinitely to produce the waveform. Firstly, is my understanding of what is going on in the FPGA/DAC correct and secondly, do you know how I could get samples to continuously stream in/out through the ethernet port? We do not need to load samples in at a very high speed, something around 20 MHz is fine and I think that is supported by ethernet.
Thank you very much for your help,
Best,
Varun
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Dear Varun,
I am delighted to hear that you got along with the reference design and could experiment a little using it.
That's correct, the host software uploads data to a firmware FIFO, the waveform memory. The firmware is then constantly feeding the converters.
You should be aware that the Ethernet link implemented in the reference design was not designed for streaming of data but only designed to handle snapshot data. It is a very minimalist layer without any kind of recovery or data integrity checks.
The FMC150 star VHDL code should be modified in order to bypass the waveform memory. You should also look at the bandwidth available on the data bus feeding the FMC150 star. You will quickly see if you can sustain pushing data from the host fast/reliable enough.
Best Regards,
Arnaud
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Thanks Arnaud.
I looked into the some of the code and we decided to go in a different direction to start. Now, I would like to read samples from the both ADCs into a file as quickly as possible. However, we need to read from both ADCs simultaneously since we're using them as a I and Q inputs. Currently, the way the app is configured, it creates a pipe to each ADCs FIFO and reads data one at a time. Is there anyway to change this to read them both at the same time?
Thanks and regards,
Varun
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Dear Varun,
The ADCs are sampling continuously but the firmware is indeed not having the signal synchronous. The firmware/software should be modified for this and this is not covered by standard technical support.
The data routers are eating any data not connected to the output, this is the most obvious modifications to be done. There are many others; get channels synchronous, get the trigger time accurate on both channels. You might also need to use a big hardware memory FIFO.
All this cannot be described in depth unless an engineering support contract is in place. Then one of our engineer will be dedicated to answer your question in details.
Best Regards,
Arnaud
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Thanks Arnaud.
I am going to try and modify the firmware to have a router with multiple inputs and outputs (maybe a s2d3 router) unlike now where it has 3 possible inputs and one output (s3d1 router). Do you have any idea who the software (C code) can be modified to accommodate this (configuring the router, reading registers etc)? I think modifying the firmware as such like you suggested will allow us to be able to read both ADCs at the same time. I noticed that you wrote the software so was wondering if you had any insight on this part.
Thanks again for your help
Varun
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Hello Varun,
The idea is that the software is able to retrieve base address of a star from the firmware for a given star ID, I think the function is called cid_getstaroffset() or something like. And then you simply write value to one of the register located on that base address.
The reference software does configure routers but in this case you will configure different routers.
Best Regards,
Arnaud
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Hey Arnuad,
Thanks I was able to modify the firmware and software to read from both ADCs synchronously. I thought everything was working but when I change the clock rate of the ADC (using the clock divider) and sample at frequencies lower than the default of 245.76 MHz (like 122.88, 61.44 etc) the data gets distorted and are no longer smooth sine waves ,or even close. I googled it and there are others with who had similar problems too but I couldn't find any solutions. Do you have any why this may be happening?
Thanks for your help
Best
Varun
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Dear Varun,
It is common to see the same signal more "stairy" when you reduce the sampling frequency. This is due to the lack of measurement points in the signal period. I would recommend you to use the buffer created by the application in Visual Analog, a free tool released by Analog Devices. This tool is handy as it computes post FFT analysis out of time domain buffers.
This could also be related to firmware related issues at low frequency, or specific chip configuration required for the new frequency. Normally any changes around the sampling frequency would call for new firmware simulations and so on.
I hope that helps,
Arnaud
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Arnaud,
The signal we get isn't "stairy" but is completely distorted so I highly doubt it is due to a lack of measurement points. I have attached an image of the output signal (output.png) as well as that of the input signal (input.png). I have also attached the input and output signals at 245.76 MHz when everything works fine (245_76.png). Do you have any idea why the signal may look like this? The signals are distorted in a similar manner at lower frequencies too. Hope this helps better understand our problem, sorry for not making it completely clear earlier.
Thanks for your help
Best
Varun
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HI,
the ADC input path is using IDELAY elements to put the data at the correct place compared to the reference clock. The idelay setting is written at run time by the host application. The value is chosen to work at the standard frequency. When you reduce the clock frequency it can happen that the clock edge shifts relative to the data window and data is sampled at the wrong moment. You will need to find the correct IDELAY value for your specific frequency.
You can change the clock IDLEY and the data IDELAY by modifying the following two parameters
else if( cid_getconstellationid() == CONSTELLATION_ID_KC705) {
printf("Found KC705 hardware\n\n");
tapiod_clk = 0x00; tapiod_data = 0x00;
}
one IDELAY tap is approximately 75 ps and I suggest incrementing with steps of 3. First with the tapiod_clk. Each time checking if it has an effect on the data you sample. At some point it should become proper data. Once you continue it will become bad data again. You should choose the tapiod_clk value in the middle between the two edges where the valid window starts.
If changing the tapiod_clk does not work, you can put the tapiod_clk back to 0 and start incrementing the tapiod_data and find a valid window.
Best regards,
Erik
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Erik,
Thank you so much for this! It was extremely helpful and I am able to get sine waves now when reading from the ADC at different frequencies, even though it took a while to find the magic numbers that worked.
I have also been trying to split up the .exe file into a init, read and write. The reason is we want to do this is so, for instance, that the read time can be reduced significantly. Ideally we'd like to call the init exe and then call the read exe repeatedly, each time reading from the ADC as quickly. I tried to do this by commenting various sections of the code but I can't get the read to work well, probably because I am ignoring some part of the code that sets up the connection. I don't close the connection (I don't call sipif_free() at the end of main) in the init exe so ideally the connection to the Xilinx FPGA should still be open (Assuming the windows OS does not close it at the termination of the exe) and the read should work. Do you have any suggestions/ pointers on how I could implement this?
Thanks and regards,
Varun
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Dear Varun,
I believe opening the hardware will cause a firmware reset, this might be a problem for you, this reset code is in the ethapi. I don't think splitting the executable in two is the right approach. What I would do if I would be you is to modify the reference application so it first do the init and then wait on a key to be pressed in a loop. Each time you press a key, you get samples and this until you press CTRL-C.
Best Regards,
Arnaud
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Arnaud,
I went with a similar approach to what you suggested so that the executable can now be controlled by an external application and perform repeated reads or writes. I am now trying to optimize the read operation so each read takes around 10-20 milliseconds. I can do this now by setting up the read operation with the sxdx_configurerouter(),fmc150_ctrl_enable_channel(), fmc150_ctrl_arm_dac(), fmc150_ctrl_sw_trigger() functions and then reading every time with the sipif_readdata() function ONLY. However the obvious problem here is that I can only read a certain number of samples total before it sipif_readdata() fails, and seems this number is 2*65536 (probably the size of the ADC FIFO). The reason I think this is so is because when I call sipif_readdata() after this, without calling any of the functions mentioned above that set up the read pipe, the ADC tries to write data out of bounds in its fifo. There must be something in one of the functions that sets up the read that makes sure this doesn't happen, maybe by sending a signal or resting a pointer or something. I tried looking for this but haven't had any luck yet.
Ideally I would like to call sipif_readdata() and then ONLY make the change that prevents this error as apposed to calling all the initializing functions again to make the reads as fast as possible. Do you have any idea where this may be? I hope I have described my problem well enough.
Thank you very much for your help so far and look forward to hearing from you.
Best,
Varun
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Hi,
you should not setup the system in a way that you can overflow the FIFO. Either read fast enough on the output of the FIFO (not possible with the Ethernet interface) or reduce the burst size to that of the maximum FIFO size.
If this reference design does not suit your application needs you have access to all the sources and you are free to modify the design.
4DSP can deliver a PCIexpress interface (400 + MB/s data transfer rate) as well as a FIFO design that uses the external DDR3 memory for storing ADC data. Please contact your local sales person if you are interested in these options.
Best regards,
Erik