4DSP Support Forum

Public Access => General Discussion => Topic started by: pnumer on July 03, 2014, 05:51 PM

Title: FMC 164/168
Post by: pnumer on July 03, 2014, 05:51 PM
I was told that the ADC chips on these boards could be configured such that they capture data out of phase with respect to each other - is that true and if so how to you configure them?
Title: Re: FMC 164/168
Post by: iklink on July 04, 2014, 06:03 AM
Dear,


This is not the case, the ADCs are all sampling on the same clock. The ADC chips don't have a feature to delay/phase shift the clock internally.
The ADC chips have settings for delaying the QDR/DDR output clocks but this is the digital domain and not the sampling clock.


Best regards,
Ingmar van Klink
Title: Re: FMC 164/168
Post by: arnaudNL on July 07, 2014, 04:21 AM
Dear Sir,


With you permission I will lock this topic, the issue being asserted I believe.


Best Regards,
Arnaud
Title: Re: FMC 164/168
Post by: arnaudNL on July 09, 2014, 07:45 AM
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.