4DSP Support Forum
Products => FMC Products => FMC110 => Topic started by: mgrand on November 08, 2013, 12:04 PM
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ISE 14.7 (64bit) returns the following error during MAP when i'm generating the bitstream of the reference design (ML605 FPGA board).
ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR
sip_fmc110_0/fmc110_if_inst/ads5400_phy_inst0/serdes_v6_inst0/bufr_inst_clk_div in clock region CLOCKREGION_X0Y3 is
driven by a CCIO adc0_clka_p_0 in clock region CLOCKREGION_X0Y1. The BUFR should be placed in the same clock region
as the CCIO or the CLOCK_DEDICATED_ROUTE constraint should be used on the net
<sip_fmc110_0/fmc110_if_inst/ads5400_phy_inst0/serdes_v6_inst0/clk_in_int>.
ERROR:Pack:1642 - Errors in physical DRC.
Does anyone know how to fix this error?
Best regards
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HI,
I was able to generate a bit file using ISE 14.6. I advice to switch to this version of ISE.
Best regards,
Erik
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Thank you for your reply.
I'm going to try ISE 14.6
Best regards
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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.