4DSP Support Forum

Products => FMC Products => FMC150 => Topic started by: JoaoFerreira on February 17, 2015, 09:19 AM

Title: Stellar IP Design
Post by: JoaoFerreira on February 17, 2015, 09:19 AM
Hello,


I have changed my fmc150 stellar ip star removing the waveform memory from DAC. Now i want to conect the ouput from ADC to DAC, which is easy to do in Stellar Ip.
Now i'm having a problem because i want to send a "copy" from the data that is passing from ADC to DAC, to zedbhost_if. I want to use the existing router, so can i just connect the output from ADC to both DAC input and router input?

I have another problem with the FMC15xAPP that i have modified. I programmed the board with the go *.bit file and everything went okay, the autonegotiation was okay too, but when i run the APP it always say "Could not open device 1000"


I already tried your APP and your bit file and it shows the samething. What is causing this issue?

Thanks
Title: Re: Stellar IP Design
Post by: lmunoz on February 17, 2015, 03:21 PM
Hi,


How did you connect the ADC to the DAC? I don't think that is easy to do, they have different rates and resolutions, did you match those and get it working? You should focus on that first once that is working sending to host is easy because it is already done. You send a trigger that starts capturing to a FIFO that gets read to the host. Streaming the ADC data to DAC requires matching the rates and resolution., if you just want to capture and repeat that is easier, just wire the adc data to that waveform repeat entity and pay attention to clock domains for commands and data.

So you haven't been able to run the reference application and bit file as provided?


Regards,
Luis
Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 17, 2015, 04:11 PM
I just removed the waveform memory from the vhdl code and in Stellar IP i conected the output of ADC to the DAC input.


I have tried to run the APP many times, and today it worked only one time.... I have already run it several times in other days and it worked, but now i'm having that error. I followed the doc explaining it. I used the jumpers in my zedboard like in the figure, but when i do it it says "done bit can't go high". If i used the jumpers in programming mode i'm capable of program the board, but then when i run the APP it says "Could not open device 1000"
Title: Re: Stellar IP Design
Post by: lmunoz on February 17, 2015, 09:10 PM
"I just removed the waveform memory from the vhdl code and in Stellar IP i conected the output of ADC to the DAC input."

That won't work, because the two devices are sampling at different rates...

There might be an error in the figure for the jumpers, follow the description in the text not the picture. Make sure you are using the bit file provided by 4dsp not the one you built. Also post your console output.

Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 18, 2015, 07:01 AM
I thought that after remove the wfm, i just have to take care with DAC and ADC frequencies when using the FMC15xAPP.


I already did everything as the doc say, with your files and the same problem occurs. I attached a photo to see.
Title: Re: Stellar IP Design
Post by: tonyku on February 18, 2015, 06:44 PM

Hi,

What is your computer IP address on the ethernet port that is connected directly to the Zedboard?


it must be set STATICALLY to 192.168.1.1 with gateway set to 192.168.1.10, subnet 255.255.255.0.


Basically the board is set to IP address 192.168.1.10 statically.   So to connect to it you have to directly connect your computer to the board and fix your computer's IP address.


Additionally you must make sure that firewalls are all OFF so that it won't block ports and connections.


Tony
Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 18, 2015, 06:48 PM
Okay i'll try tomorrow to see the firewall, because i did that IP adress configuration
Title: Re: Stellar IP Design
Post by: tonyku on February 18, 2015, 08:14 PM


Also, if everything is setup properly on the network side, you should be able to PING the card.  If firewall is off, ip addresses are set correctly and you can't ping it, then this suggest issue with the firmware build.


Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 19, 2015, 08:14 AM
I tried what you said, the problem wasn't solved.
Then i changed the ethernet cable and everything works fine. :S


Now, i ask some help because lmunoz said that the changes i have made to the vhdl code wasn't sufficient to do what i want to.


I thought that i only had to remove thw waveform memory and then change the FMC15xAPP. I would apreciate if you could give some hints about this situation.



Title: Re: Stellar IP Design
Post by: arnaudNL on February 20, 2015, 06:48 AM
Dear Sir,


You are trying to feed a ADC output to a DAC. This is fine but this assumes that:


1) The sampling frequency of both ADC and DAC are the same.
2) The resolution is the same.
3) The sample justification is the same.


All the three above are not the case in the standard reference design. Changing the sampling frequency would be about experimenting settings in the clock tree device and I believe you want to place a user processing star between the ADC and the DAC in order to modify the DAC output in a way it can be fed to the DAC (resolution and justification of the samples).


I hope that helps!


Best Regards,
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 20, 2015, 12:49 PM
Thanks for the help.


So you are saying that i can change the sampling frequency of the DAC na dmake it equal to the ADC? Or it isn't possible and i have to change it with a processing star?
Title: Re: Stellar IP Design
Post by: arnaudNL on February 23, 2015, 05:04 AM
Dear Sir,


It will be extremely difficult to modify the design if you don't understand the hardware architecture first. You need to first look at the DAC (DAC3283) and ADC (ADS62P49) integrated circuits in order to check its operation modes. The DAC has interpolation modes so you can have the DAC running twice as fast as the ADC clock. The the clock tree device, the CDCE72010 is in charge of dividing the VCO loop's output frequency by n. Figure 5 in the FMC150 user manual provides a diagram of the clock tree.


Chapter 5 of the user manual describes how to control the FMC150.


If you are interested, 4DSP can develop such a firmware, the ADC go to the DAC through a user processing star and you can implement your user processing in that star. Is it a path you are interested to follow? I would expect 3-5 man days is required in order to do that on our side. If you are interested I can get you in touch with one of our sales agent.


I hope that helps!


Best Regards,
Arnaud







Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 23, 2015, 06:35 AM
Hum ok but the FMC150 user manual doesn't describe clearly that work.
I read that we can give an external clock, we can use it as sampling clock for both ADC and DAC?


Probably these questions are pretty obvious for you, but for the people trying to learn about your firmware these questions are not clear.
Title: Re: Stellar IP Design
Post by: arnaudNL on February 24, 2015, 07:13 AM
Dear Sir,


As explained already, modifications done of the free of charge reference design are not supported by standard technical support. You will need to purchase an engineering support contract to get detailed help as per your expectations.


At this stage I think you should try and experiment because this is part of engineering. Maybe it sounds a bit short but we have sold more than 7000 FMC150s over the last 4 years and other customers where able to integrate this hardware solely referring to the FMC150 User Manual.


If you want everything done easy and step by step guidance on how to modify the reference design, an engineering support contract is required. Are you interested by this path?


Best Regards,
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on February 24, 2015, 07:21 AM
I'll try to figure out on my own
Title: Re: Stellar IP Design
Post by: arnaudNL on February 26, 2015, 07:40 AM
Dear Sir,


Are you able to move forward? Is there anything I can do in more?


Best Regards,
Arnaud
Title: Re: Stellar IP Design
Post by: arnaudNL on March 02, 2015, 06:37 AM
Dear Sir,


I appreciate the fact I could not do more as per our policy and regulation but I want to followup with you. Are you able to move forward?


Best Regards,
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 02, 2015, 08:53 AM
Well, i was studying my problem and i concluded that the ADC is working at 250 MHZ and the DAC is working at 125 MHZ.


Now, i'm trying to understand how i should proceed to make the sample frequency equal.
Title: Re: Stellar IP Design
Post by: arnaudNL on March 06, 2015, 09:50 AM
Dear Sir,


Let me try to formulate a few pointers for you. Both DAC and ADC clocks are coming from the clock tree device. I might be wrong, I haven't looked much around the design aspects but I believe the interpolation in the DAC is set to 4x because the ADC is running twice as fast and there is a dual data rate bus in the line.


I am not sure what is the maximum DAC speed on the FMC150 maybe you cannot double it up. Then you would want to get the ADC clock half down.




I hope that helps!


Best Regards,
Arnaud







Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 06, 2015, 11:33 AM
Hello


I finally got the cables to make some experiments.


And with your current design i could see in the txt files the samples inputed in the DAC and the samples outputed from ADC. I compared the samples from both files and i saw that the frequency from the output digital sinewave of ADC was half of the input digital sinewave in DAC.


But that makes sense because the ADC is working two times faster then DAC.


So i already have been looking the clocktree and i was able to reduce the ADC sample frequency to make it equal to the DAC sample frequency. After that i run the APP with that differences and what i get in the adc txt files is completely different from what is supposed.


I don't know why when ADC and DAC are playing with the same sample frequency the results are wrong...



Title: Re: Stellar IP Design
Post by: arnaudNL on March 09, 2015, 05:32 AM
Dear Joao,


Can you post your txt file when you change the DAC clock? I am not sure I can do much but at least point out obvious things. Can you also in the same time tell me what are you output frequencies from the clock tree reported by the application, for DAC PHY and DAC REF. Can you also let me know if you have changed anything around the interpolation settings in the DAC?


Thanks,
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 10, 2015, 07:27 AM
I used your ref design as you gave, the only thing that i have changed was the adc frequency to be equal to the DAC. So i made the DAC phy freq and ADC phy freq the same.


The files and the frequencies are attached. It give some pattern erros and i don't know why.
Title: Re: Stellar IP Design
Post by: lmunoz on March 11, 2015, 10:30 PM
The ADC errors might be because the IODELAY need to change when the frequency changes.


I suggest you run the simulation with your changes and see if that is working.
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 13, 2015, 08:04 AM
Ise simulation?


But i changed the frequency, changing the Fmc15xApp code.
Title: Re: Stellar IP Design
Post by: arnaudNL on March 13, 2015, 08:46 AM
Dear Joao,


Luis means that changing the sampling frequency require extra steps, simulating if the firmware can work with these new parameters. This is a standard firmware design iteration, timing in design may or may not work for all sampling frequencies.


Best Regards.
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 13, 2015, 11:36 AM
Ok. I have another question too. While using your ref.design i noticed that conecting the output of DAC to the oscilloscope, it shows always the sinewave that was sent to the waveform memory. My question is, how the DAC is always "playing" that sinewave? It is stored in some BRAM or it is always reading the same waveform memory?



Title: Re: Stellar IP Design
Post by: arnaudNL on March 13, 2015, 11:52 AM
Dear Joao,


There is a waveform memory in the FMC150 star, a function sets the burst size and the firmware loop-back to begin of waveform memory when the counters reaches burst size. The software uploads samples to the DAC waveform memory and arm the board so it starts playing. It looks like continous because the size waveform has a perfect wrap around.


The module in charge of that in the firmware is located in the fmc150 star source code, dac3283_wfm.vhd


I hope that helps!


Best Regards,
Arnaud



Title: Re: Stellar IP Design
Post by: lmunoz on March 13, 2015, 11:54 AM
Yes, the sine wave gets stored in a BRAM and continuously played back.

In code you can see there is an entity called sip_fmc150.vhd, the data from the host comes in on two signals for the first dac

   dac0_in_dval                            : in    std_logic;
   dac0_in_data                            : in    std_logic_vector(63 downto 0);

That goes into an entity called dac3283_wfm.vhd, "Wave Form Memory". Once it is saved using commands you can play it back continuously, that is what the reference app does.

All this can be simulated and makes it easier to understand how everything is working, the CID documentation says

From the Tcl Console (View -> Panels -> Tcl Console) run the following command:
source ../../simulate/isim/isim.tcl


Then you can simulate and trace the data around. My suggestion is to do everything in steps.

1) Simulate the design as provided and get a basic understand how it is working.
2) Match the frequencies of the DAC and ADC and make sure it is still working.
3) Connect the ADC to the DAC and again confirm those changes are working
4) Synthesize

There are many reasons why things might not be working and simulating is an easy to see what is happening. For example there is an dac3283_phy.vhd entity that accepts data to send to the DAC. There is an ads62p49_phy entity that receives data coming from the ADC. In simulation you can see what type of data is going in and out and that is what you need to get to match.




Title: Re: Stellar IP Design
Post by: arnaudNL on March 16, 2015, 05:18 AM
Dear Joao,


Was the information sufficient, can we go ahead and close this topic?


Best Regards,
Arnaud
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 16, 2015, 12:54 PM
I have a few more questions.


I already talked about the DAC and i understood that it is always reading the same data from the BRAM. What about the ADC? I already tried to input a sinewave from a function generator and it captured 1024 samples because it is what the ref. design is doing. So my question is, the ADC is always trying to acquire some data? Or it just acquires when i play the Fmc15xAPP?


The other question is, from my point of view the ref. design is using the FMCAPP to send commands and  comunicating with zedboard and FMC150, so it is possible to pass this FMCAPP to the processor of Zedboard? What i'm trying to say is, using the processor of zedboard we could adapt the FMCAPP to play the routine we want. Is this possible?


Best regards
Title: Re: Stellar IP Design
Post by: arnaudNL on March 17, 2015, 07:37 AM
Dear Joao,


The ADC always output samples but the acquisition only happens after sending a software (or hardware) trigger.


Moving the FMC150App code to Zynq is doable, will require a bit of efforts but something that can be done.


I hope that helps,


Best Regards,
Arnaud


PS: We are moving away from the forum towards a ticket system on support.4dsp.com, feel free to register there and post continuation posts if you need. I assume I can close this topic in the meanwhile?[size=78%] [/size]
Title: Re: Stellar IP Design
Post by: JoaoFerreira on March 17, 2015, 12:16 PM
Ok you can close this topic. I'll use the ticket system
Title: Re: Stellar IP Design
Post by: arnaudNL on March 19, 2015, 06:17 AM
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.