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Changing the ADAC Sampling Clock in the ML605 Reference Design

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John Baker:
We are having all sorts of fun with the reference design. It performs pretty well. But now it is time to increase the sample rate so we can operate with our intended IF. Does 4DSP have any tips or application notes so we can benefit from the design team's knowledge of the FMC150?
Thanks,
John

arnaudNL:
Hello John,
 
Happy to hear the reference design suited your needs up to now. We do not have much guidelines. Increasing the sample rate might cause timing issues which would need to be asserted by the designer.
 
Best Regards,
 
Arnaud

John Baker:
Arnuad,

Yes, I can see that there is little in way of guidelines on the 4DSP Website. I understand that changing the clock rates of the FMC150 devices will impact the FPGA design. I guess what I was looking for is some insight the FMC design team might have regarding the expected performance of the FMC-150 and any know pitfalls we should avoid during our development.

Thanks,
John

JohnE:
I would very much like to see the same. I have an immediate, specific application requiring a sample rate of approx. 250Ms/s (yes, 245.76 is adequate) on the A/D and the D/A.

First test is a simple loopback from a modulator through the DAC, through the MMCX cables, back through the ADC, and through the demodulator.

arnaudNL:
Dear Avnet users,
 
Maybe formulate questions and precise requests and I will see what I can do.
 
Best Regards,
 
Arnaud

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