Topic: FMC168 External Trigger (Continues from last time)  (Read 2666 times)

roengrut March 11, 2015, 11:45 PM

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Dear Arnaud,

I am sorry for replying to you so late. I and my colleague have been busy with other work and also trying with what you suggested with our FMC168 as you replied me in

http://www.4dsp.com/forum/index.php?topic=3657.0

I also attached a PDF file showing the software code we run the FMC. We also draw the picture of the result in another attached file here. The result seems to be working for the external trigger of (approximately) 60 Hz with burst size of 1024. In this test we could read data from all 8 channels perfectly by applying 8 consecutive trigger pulses. When we tried with the trigger source with higher frequency (with the same software), in the picture we applied 244 kHz (we calculated and found that a frequency just slightly higher than 244 kHz is the maximum that the trigger can be), we can capture data only from the first channel (ADC0) but 8 times consecutively. Is there anything wrong with what we tried? Should we modify something else or is there any limitation ?

Thank you very much for your time. I hope to hear from you again next time.

Best Regards,

Roengrut

ebarhorst March 13, 2015, 07:17 PM (#1)

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Hi roengrut


I suspect that your clock rate is 250MHz? With a trigger rate of 244KHz you are almost sampling the data continuously. the time between two triggers is 4.098us. The time to capture 102 samples at 250MHz takes 4.096 us. So if your trigger rate is any faster you will miss one trigger while it is busy capturing the previous trigger.
Best regards,
Erik

roengrut March 16, 2015, 03:52 AM (#2)

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Hello Erik,

Thanks for your advice. We realize that the trigger rate of 244 kHz will be the maximum rate. Anyway, we would like to ask for your suggestions on the following scenarios:

1) Can we capture data on ALL 8 channels with 1 trigger pulse with the trigger rate of > 10 MHz ? In this case, we know that the burst size need to be smaller than 1024. So, it can be any small number. Please correct us if we are incorrect.

2) If the question number 1) can be achieved, for capturing data on all 8 channels, what should be an appropriate range for "burst number". In the case that if we would like a burst size < 128 (any number), what should be a busrt number (x), such that x > 1 ?

Thank you very much for your time again. I look forward to your suggestion as always.

Best Regards,

Roengrut

ebarhorst March 16, 2015, 08:09 AM (#3)

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Hi Roengrut,


we typically do not test burst sizes that small. I think that the burst size should be a multiple of 4 samples. The best way to proceed for you is to experiment. If there are some issues you do have the source code of the FPGA available to modify it to suit your application. It is also possible to have 4DSP make modifications or design suggestions in case there is an extended support contract in place.


Best regards,
Erik

roengrut March 18, 2015, 03:05 PM (#4)

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Hi Erik,

Thank you very much. We will try to do some experiment and also modify the firmware for our case. If there are something we really need for more and complicated modifications, we will certainly contact you for more help or extended support.

Best Regards,

Roengrut

arnaudNL March 20, 2015, 05:12 AM (#5)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.