Topic: CONFUSION IN THE USER MANUAL OF FMC112  (Read 4767 times)

mhada March 04, 2015, 05:50 AM

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Hi,

We have gone through the user manual of FMC112 i.e. UM012 and we are confused as to what exactly the trigger signals doing and where exactly are they connected in the block diagram? How they are helping in customized sampling?

Again we are not clear as to what is the role of VADJ from the user manual. Kindly explain.

Is the EEPROM and the ADT7411 sharing common bus - I2C on board or not?


Thanks and Regards.

Mohit Hada

arnaudNL March 06, 2015, 08:55 AM (#1)

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Dear Sir,


- The trigger goes to the FPGA through the FMC connector. It allows you to decide when you trigger, it is an external trigger, similar to what a trigger input is on an oscilloscope.
- VADJ is defined by the FMC specification. It is stands for Voltage ADJustable. This voltage comes from the FPGA carrier board and power some IOs. Generally VADJ also power the FPGA banks so there is compatibility between the FMC board IOs and the FPGA IOs.
- Yes, both EEPROM and ADT7411 shares the same i2c bus. The i2c bus pins on the FMC connector is also defined by the FMC specifications.


I hope that helps!


Best Regards,
Arnaud

mhada March 06, 2015, 09:19 AM (#2)

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Hi Arnaud,

Thanks for the reply.

You mean to say that Trigger signal enters through the front panel samtec connector and passes directly to FPGA [AND VICE VERSA FOR TRIGGER OUT] without being electrically touched on the FMC cards.

Again can you tell us what all IOs are powered by VADJ?


Thanks and Regards.

Mohit Hada

iklink March 09, 2015, 06:56 AM (#3)

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Dear,


The trigger input goes from the panel connector to a single-ended to LVDS converter and is then directly connected to CLK1_M2C_P/N of the FMC connector. The recommended logic standard is LVTTL. For the trigger output, please refer to section 4.4.2 of the user manual (r1.6).


Please refer to table 9 in the user manual to see which IOs are powered by VADJ. For more information about VADJ I would recommend you to read FMC related documentation such as AV57.1.


Best regards,
Ingmar van Klink
4DSP

arnaudNL March 10, 2015, 12:21 PM (#4)

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Dear Mohit,


Please let me know if the information was sufficient and if we can go ahead and close this specific topic.


Best Regards,
Arnaud

mhada March 11, 2015, 02:22 AM (#5)

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yes arnaud,

Thanks for support.

Thanks and Regards.

Mohit Hada

mhada March 11, 2015, 07:14 AM (#6)

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Hi Arnaud,

One more final doubt before you actually close the post i.e. why the driver circuit and ADC inputs have been in reverse polarity i.e. a polarity twist. What is the intention of doing this?

 
Thanks and Regards.

Mohit Hada

arnaudNL March 11, 2015, 12:03 PM (#7)

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Mohit,


Yes, we took the decision to get better signal integrity on the PCB. It was better to swap the pairs in order to get a better routing.


This is of course not a mistake, this was done for the sake of effective number of bits and general integrity.


Let me know if I can close the topic.


Best Regards,
Arnaud

mhada March 12, 2015, 02:57 AM (#8)

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ok thanks.


Thanks and Regards.

Mohit Hada

arnaudNL March 12, 2015, 06:29 AM (#9)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.