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ZC702 + 2 FMC30RF

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fjoao012:
Hello,
I'm currently trying to build a design in the ZC702, where it is connected to 2 (two) FMC30RF, one in each FMC LPC port, but now I'm having some issues concerning the design:
I started with your StellarIP design, and edited it to have the two boards; after that, I opened ISE, and after some tweaks to the VHDL to implement all like I wanted, the ISE design tells me that the design is unfeasible due to the overmapping of RAMB36E1.
Basically, I just duplicated the FMC30RF board in this design, and the quantity of RAMB36E1 used in the original project doubled, turning the design impossible. With this, I assumed that all the RAMB36E1 is being used just in the FMC30RF..
In the documents you provided, you say that is possible to make a MIMO architecture, and I wanted to ask you some things:

1) What is your recommendation regarding such a design? Should I use a multiplexer to receive information from the two boards or should I use just one axi bus? Or Should I just follow a completely different approach to this problem?
2) Is there any way I can change the utilization of all the RAMB36E1 provided in your design? For example, turning the RAMB36E1 to RAMB18E1 or any other thing?
3) Do you have any documentation/tutorials/examples regarding this "one ZC702-to-two FMC30RF" design I'm trying to build?

Thank you,
Joao

arnaudNL:


Dear Joao,


1) I think you one a data merger and two FMC30RF stars connected to it. This would provide you with a stream of data coming from both stars. Unfortunately I don't have such a star available out of the shelve.
2) I believe there are input/output FIFOs on the tx/rx wormhole connecting to sip_fmc30rf as well as waveform memory. It might be that the zynq chip don't have enough resources in order to double that up. Try to divide by two the resource of one FMC30RF star and then it should work.
3) No, the only thing we have is the reference for one FMC30RF. Using two FMC30RF together is more about architectural difficulties so it is not easy to document. But anyway, we are here to provide you with pointers when you need.


Best Regards,
Arnaud


 

arnaudNL:
Dear Joao,


Do you still need this topic open? do you need extra information about this specific issue before I close this topic?


Best Regards,
Arnaud

fjoao012:
Hey Arnaud,
I'm interested in the 2) solution you provided, I had already thought about it but I didn't acknowledge how to make that yet. I'm trying to use Core Generator (by Xilinx) on the sip_zc702 module you provided from StellarIP. Is this the way, or do you recommend to do it differently?

Thanks,
Joao

arnaudNL:
Dear Joao,


Yes, correct. There are many cores in the star_lib\sip_fmc30rf\vhdl\z7\xilinx folder containing FIFOs. There are ise project as well as xcos for these.


Best Regards,
Arnaud

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