Topic: Stellar IP Design  (Read 31903 times)

arnaudNL February 26, 2015, 07:40 AM (#15)

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Dear Sir,


Are you able to move forward? Is there anything I can do in more?


Best Regards,
Arnaud

arnaudNL March 02, 2015, 06:37 AM (#16)

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Dear Sir,


I appreciate the fact I could not do more as per our policy and regulation but I want to followup with you. Are you able to move forward?


Best Regards,
Arnaud

JoaoFerreira March 02, 2015, 08:53 AM (#17)

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Well, i was studying my problem and i concluded that the ADC is working at 250 MHZ and the DAC is working at 125 MHZ.


Now, i'm trying to understand how i should proceed to make the sample frequency equal.
  • « Last Edit: March 05, 2015, 11:51 PM by JoaoFerreira »

arnaudNL March 06, 2015, 09:50 AM (#18)

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Dear Sir,


Let me try to formulate a few pointers for you. Both DAC and ADC clocks are coming from the clock tree device. I might be wrong, I haven't looked much around the design aspects but I believe the interpolation in the DAC is set to 4x because the ADC is running twice as fast and there is a dual data rate bus in the line.


I am not sure what is the maximum DAC speed on the FMC150 maybe you cannot double it up. Then you would want to get the ADC clock half down.




I hope that helps!


Best Regards,
Arnaud







JoaoFerreira March 06, 2015, 11:33 AM (#19)

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Hello


I finally got the cables to make some experiments.


And with your current design i could see in the txt files the samples inputed in the DAC and the samples outputed from ADC. I compared the samples from both files and i saw that the frequency from the output digital sinewave of ADC was half of the input digital sinewave in DAC.


But that makes sense because the ADC is working two times faster then DAC.


So i already have been looking the clocktree and i was able to reduce the ADC sample frequency to make it equal to the DAC sample frequency. After that i run the APP with that differences and what i get in the adc txt files is completely different from what is supposed.


I don't know why when ADC and DAC are playing with the same sample frequency the results are wrong...



arnaudNL March 09, 2015, 05:32 AM (#20)

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Dear Joao,


Can you post your txt file when you change the DAC clock? I am not sure I can do much but at least point out obvious things. Can you also in the same time tell me what are you output frequencies from the clock tree reported by the application, for DAC PHY and DAC REF. Can you also let me know if you have changed anything around the interpolation settings in the DAC?


Thanks,
Arnaud

JoaoFerreira March 10, 2015, 07:27 AM (#21)

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I used your ref design as you gave, the only thing that i have changed was the adc frequency to be equal to the DAC. So i made the DAC phy freq and ADC phy freq the same.


The files and the frequencies are attached. It give some pattern erros and i don't know why.
  • « Last Edit: March 10, 2015, 07:33 AM by JoaoFerreira »

lmunoz March 11, 2015, 10:30 PM (#22)

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The ADC errors might be because the IODELAY need to change when the frequency changes.


I suggest you run the simulation with your changes and see if that is working.

JoaoFerreira March 13, 2015, 08:04 AM (#23)

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Ise simulation?


But i changed the frequency, changing the Fmc15xApp code.

arnaudNL March 13, 2015, 08:46 AM (#24)

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Dear Joao,


Luis means that changing the sampling frequency require extra steps, simulating if the firmware can work with these new parameters. This is a standard firmware design iteration, timing in design may or may not work for all sampling frequencies.


Best Regards.
Arnaud

JoaoFerreira March 13, 2015, 11:36 AM (#25)

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Ok. I have another question too. While using your ref.design i noticed that conecting the output of DAC to the oscilloscope, it shows always the sinewave that was sent to the waveform memory. My question is, how the DAC is always "playing" that sinewave? It is stored in some BRAM or it is always reading the same waveform memory?



arnaudNL March 13, 2015, 11:52 AM (#26)

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Dear Joao,


There is a waveform memory in the FMC150 star, a function sets the burst size and the firmware loop-back to begin of waveform memory when the counters reaches burst size. The software uploads samples to the DAC waveform memory and arm the board so it starts playing. It looks like continous because the size waveform has a perfect wrap around.


The module in charge of that in the firmware is located in the fmc150 star source code, dac3283_wfm.vhd


I hope that helps!


Best Regards,
Arnaud



lmunoz March 13, 2015, 11:54 AM (#27)

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Yes, the sine wave gets stored in a BRAM and continuously played back.

In code you can see there is an entity called sip_fmc150.vhd, the data from the host comes in on two signals for the first dac

   dac0_in_dval                            : in    std_logic;
   dac0_in_data                            : in    std_logic_vector(63 downto 0);

That goes into an entity called dac3283_wfm.vhd, "Wave Form Memory". Once it is saved using commands you can play it back continuously, that is what the reference app does.

All this can be simulated and makes it easier to understand how everything is working, the CID documentation says

From the Tcl Console (View -> Panels -> Tcl Console) run the following command:
source ../../simulate/isim/isim.tcl


Then you can simulate and trace the data around. My suggestion is to do everything in steps.

1) Simulate the design as provided and get a basic understand how it is working.
2) Match the frequencies of the DAC and ADC and make sure it is still working.
3) Connect the ADC to the DAC and again confirm those changes are working
4) Synthesize

There are many reasons why things might not be working and simulating is an easy to see what is happening. For example there is an dac3283_phy.vhd entity that accepts data to send to the DAC. There is an ads62p49_phy entity that receives data coming from the ADC. In simulation you can see what type of data is going in and out and that is what you need to get to match.




arnaudNL March 16, 2015, 05:18 AM (#28)

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Dear Joao,


Was the information sufficient, can we go ahead and close this topic?


Best Regards,
Arnaud

JoaoFerreira March 16, 2015, 12:54 PM (#29)

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I have a few more questions.


I already talked about the DAC and i understood that it is always reading the same data from the BRAM. What about the ADC? I already tried to input a sinewave from a function generator and it captured 1024 samples because it is what the ref. design is doing. So my question is, the ADC is always trying to acquire some data? Or it just acquires when i play the Fmc15xAPP?


The other question is, from my point of view the ref. design is using the FMCAPP to send commands and  comunicating with zedboard and FMC150, so it is possible to pass this FMCAPP to the processor of Zedboard? What i'm trying to say is, using the processor of zedboard we could adapt the FMCAPP to play the routine we want. Is this possible?


Best regards