Topic: Configuring ADC  (Read 9488 times)

karen February 16, 2015, 04:53 AM

  • Member
  • *
  • Posts: 20
Hi,


I want the FMC112 start sampling right after FPGA programmed without the need of any PC-side software initialization. could you please give me some advise how to accomplish that? ie. which registered should be initialized in FPGA??




tnx

arnaudNL February 16, 2015, 11:18 AM (#1)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
Dear Karen,


We do not have register tables with all the values but we do have a reference software writing to all these registers through the reference firmware; fmc116_clocktree.cpp, fmc116_adc.cpp, etc..


I hope that helps!


Best Regards,
Arnaud





karen February 17, 2015, 03:41 AM (#2)

  • Member
  • *
  • Posts: 20
Arnaud, thanks for your reply,


What I want is to know exactly what the reference software cpp files does on firmware configuration registers.




Since I changed the MAC engine to achieve higher throughput, I'm no longer able to communicate through your provided software, I need to have ADC start acquisition right after FPGA is programmed.




I'll be so grateful if you could help me on the issue.

arnaudNL February 17, 2015, 02:05 PM (#3)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
Dear Karen,


As explained already, the cpp has very descriptive sequence many customers been able to use as a base. You may need to go back using the default reference software and default firmware in order to do that.


What I would do myself, as 4DSP does not have init tables, would be to modify sipif.cpp in order to create a table with all the writes done; which address and what value.


Another option would be to have 4DSP create you the init table for you but there you would expect some costs involved.


Please let me know how you would like to process!


Best Regards,
Arnaud

arnaudNL February 20, 2015, 11:59 AM (#4)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
Dear Karen,


Please let me know if there is anything more I can do before to close this topic.


Best Regards,
Arnaud

karen February 22, 2015, 02:43 AM (#5)

  • Member
  • *
  • Posts: 20

because you are the writer of the code on PC side, my impression was you should be crystal clear what your code does on FPGA!


feel free to close the topic.

arnaudNL February 23, 2015, 07:10 AM (#6)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
Dear Karen,


Don't be fooled by the appearance. I haven't wrote the code. The code was based on a framework I wrote back in 2010 and was created on October 7 2011 by an engineer in Austin. The engineer was probably a bit shy and kept my names in there...


I feel sorry I could not meet your expectations and provide you a table we don't have. I offered you two options at the time, create the table on your side or get 4DSP to provide you with this table. In this case someone would need to sit and create this table and this will have a cost.


Please keep in mind the reference design is free of charge so do the standard technical support forum. The reference design comes in source code and with documentation.


Best Regards,
Arnaud







arnaudNL February 23, 2015, 07:10 AM (#7)

  • 4DSP Staff (EU)
  • Administrator
  • Member
  • *****
  • Posts: 7110
This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.