Topic: FMC110 on v6sx315t ff1156  (Read 4747 times)

bzhong February 11, 2015, 08:20 PM

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Hi,


I'm trying to integrate the FMC110 on a v6sx315t FPGA, but I am seeing some placement errors with the clock pins.  The adc0 clock uses pin AE33 (fmc_ha_p/n[1]) which is an MRCC pin on the FPGA and it is sent to a multiple of buffers in the serdes_v6 file.  See below, where adc0 clock pin is driving CLK_IN_P and CLK_IN_N:



-- Create the clock logic
ibufgds_inst_clk : IBUFGDS
generic map (
  DIFF_TERM  => TRUE,   
  IOSTANDARD => "LVDS_25"
)
port map (
  I  => CLK_IN_P,
  IB => CLK_IN_N,
  O  => clk_in_int
);


-- High Speed BUFIO clock buffer
-- BUFIO replaced by BUFG to reach ISERDES spread over multiple banks in different columns
bufg_inst_clk : BUFG
port map (
  I => clk_in_int,
  O => clk_in_int_buf
);
       
-- BUFR generates the slow clock
bufr_inst_clk_div : BUFR
generic map (
  SIM_DEVICE => "VIRTEX6",
  BUFR_DIVIDE => "4"
)
port map (
  I   => clk_in_int,
  O   => clk_div_tmp,
  CE  => '1',
  CLR => CLK_RESET
);


-- Slow clock is driven by a BUFG to equalize delays between fast and slow clock,
-- this is necesary to properly sync/reset ISERDES' spread over multiple banks in different columns
bufg_inst_clk_div : BUFG
port map (
  I => clk_div_tmp,
  O => clk_div
);


The problem is that the tool places the BUFGCTRL at BUFGCTRL_X0Y28.  Since the fmc_ha_p[1] pin is a mrcc pin in clock region x0y1, the tool can't route these (I'm guessing).  The following is the error message that I see:



ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGCTRL site pair. The clock IOB component <io_fmc_ha_p(1)> is placed at site <AE33>. The corresponding
   BUFGCTRL component
   <ic_example_top_i/app_inst/fmc_4dsp_wrapper/u_fmc110_top/u_sip_fmc110/fmc110_if_inst/ads5400_phy_inst0/serdes_v6_inst
   0/bufg_inst_clk> is placed at site <BUFGCTRL_X0Y28>. The clock IO can use the fast path between the IOB and the Clock
   Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest dedicated path to all BUFGCTRL
   sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in
   its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub
   optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
   the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to override this clock rule.
   < NET "io_fmc_ha_p(1)" CLOCK_DEDICATED_ROUTE = FALSE; >


Any ideas on solving this?  I also tried the "CLOCK_DEDICATED_ROUTE = FALSE" constraint but that gave me a different error.


Thanks,
Billy
  • « Last Edit: February 11, 2015, 08:24 PM by bzhong »

rzandvliet February 13, 2015, 06:48 AM (#1)

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Dear sir,

ISE has placed the bufg_inst_clk in the top-half of the FPGA. Since the IBUFGDS is located in the bottom-half it cannot reach the bufg_inst_clk. This issue can be solved by locking the bufg_inst_clk to a BUFG that is located in the bottom-half of the FPGA. This can be done with the following UCF constraint:

INST "bufg_instance_name" LOC = BUFGCTRL_X0Y12;

Please let me know if you have any questions.

Best regards,
Rémon Zandvliet

bzhong February 13, 2015, 12:38 PM (#2)

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After adding that constraint, I still get the same error.



ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGCTRL site pair. The clock IOB component <io_fmc_ha_p(1)> is placed at site <AE33>. The corresponding
   BUFGCTRL component
   <ic_example_top_i/app_inst/fmc_4dsp_wrapper/u_fmc110_top/u_sip_fmc110/fmc110_if_inst/ads5400_phy_inst0/serdes_v6_inst
   0/bufg_inst_clk> is placed at site <BUFGCTRL_X0Y12>. The clock IO can use the fast path between the IOB and the Clock
   Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest dedicated path to all BUFGCTRL
   sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in
   its half of the device (TOP or BOTTOM).

rzandvliet February 16, 2015, 11:47 AM (#3)

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Dear Sir,

I’ve checked your device and it seems that in Virtex-6 devices only MRCCs located in the center right/left column I/O can drive BUFGs. Since your MRCC pin is located in the left outer side of the device it is not possible to connect to a BUFG directly. What you can try to do is to first connect the clock input to a BUFR and to connect the clock output of the BUFR to a BUFG.

Unfortunately I am not able to help you further at this moment since this goes beyond standard support. If you need more help with solving this issue I would like to ask you to contact sales to discuss the possibilities of a more extensive support contract.

Best regards,
Rémon Zandvliet

bzhong February 16, 2015, 11:56 AM (#4)

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Currently the connection is:


CLK_IN -> IBufgds -> Bufg -> SERDES
                                            -> Bufr (div4) -> bufg


Are you saying I should do this:



CLK_IN -> IBufgds -> Bufr -> Bufg -> SERDES
                                                         -> Bufr (div4) -> bufg

rzandvliet February 17, 2015, 06:54 AM (#5)

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Yes I suggest to implement that setup.

Best regards,
Rémon Zandvliet

arnaudNL February 20, 2015, 12:00 PM (#6)

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Dear Sir,


I believe the information was sufficient, is there anything more we can do before to close this topic?


Best Regards,
Arnaud

arnaudNL February 24, 2015, 07:54 AM (#7)

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Dear Sir,


I will close this topic in 24 hours unless you have something to add.


Best Regards,
Arnaud

arnaudNL February 26, 2015, 07:37 AM (#8)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.