Topic: fmc161 vivado project  (Read 8418 times)

leongnrl February 02, 2015, 08:29 PM

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I am wonder if there is an vivado project for fmc161. There seems to be a timing/trimming problem when I import the ISE project to vivado.

arnaudNL February 03, 2015, 07:05 AM (#1)

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Dear Sir,


Unfortunately not. We only have support for KC705 and VC707 on ISE. Try to look at the "FLATTEN HIERARCHY" option in Vivado it should be set to "NONE".


I believe you can try to send this command in the TCL prompt: set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none


Maybe this will help, otherwise I don't know. You can still try to create a Webcase with xilinx to ask them some pointers.


Best Regards,
Arnaud

leongnrl February 03, 2015, 12:23 PM (#2)

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I have tried flatten hierarchy to none but no luck. I am suspecting there is a cross clock domain problem in the code which is ignored in ISE but failed on vivado since vivado deals with timing constraint more strictly.I either got the project compiled but with timing error, or compiled fine with addition clock domain isolation constraint but the fmc161 doesn't run.

arnaudNL February 03, 2015, 01:57 PM (#3)

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Dear Sir,


Yes, indeed maybe the timing error is an expected error and a timing ignore is required.


Could you please provide me with the timing report so I can quickly ask a firmware engineer to have a look. I cannot do much but I will give that a try. Anything that could be useful like a detailed error would be a plus.


Best Regards,
Arnaud

leongnrl February 04, 2015, 07:58 PM (#4)

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Vivado treats all clock as synchronized to each other unless otherwise specified. At first I got all inter clock timing error between all the clocks. Then, I set all the clocks as asynchronous clock. This get rid of all the timing error but the design doesn't work. To me, it is more like some signals or components are being auto trimmed out but I am not sure what the actual cause it. Can 4dsp look into this problem?

arnaudNL February 05, 2015, 05:08 AM (#5)

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Dear Sir,


The only way we can look into that would be to have one of our firmware engineers doing the steps for you. I believe we could get that done in 2-3 man days and obviously this has a cost; I believe nowadays the man days are around 1000$. It might look overkill but we will make sure everything works smooth and the design will be properly tested.


Another option would be to describe what "doesn't work" so I can discuss that with firmware engineers and provide you with some pointers.


Let me know how you want to proceed, I can get you in touch with a sales person if you wish.


Best Regards,
Arnaud



leongnrl February 05, 2015, 12:38 PM (#6)

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I will check with my supervisor regarding to money.

So what I did so far was importing the ISE project 445_vc707_fmc161 to vivado 2014.3. All the sources files are imported to vivado except the constraint file. I create a xdc file with all the pinout out without putting any timing constraint yet. Then I use the constraints wizard, which auto detects the clocks, to enter the timing. Afterward I got lots of inter-clock timing error, so I create another asynchronous clock group timing between adc clocks, mac transceiver clock, and sysclk. After that I got timing error for two of the generated clock from sysclk, so I create a false path between the two.

Got the project compile without timing error, program device, run the fmc161app, couldn't obtain sipcid table error. If I program the device with the bit file that I generated from ISE, everything works.

I put debug core to check adc_phy_i_data but the debug core failed to trigger and seems like there is no clock to the debug core. The clock of adc_phy_i_data is adc_phy_i_clk.

Where should I look at now? Any suggestion will be greatly helpful.

lmunoz February 06, 2015, 01:01 PM (#7)

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If you are getting a couldn't obtain sipcid table error then the problem is the host interface IP block, so focus on that first. Can you send the xdc file you are using. Converting from ucf to xdc is pretty straightforward for most our designs so if there is an issue with it I will be able to send you the fixed version.

leongnrl February 06, 2015, 01:28 PM (#8)

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I am sure that the sipcid table error is not cased by host interface IP blocking since my ISE bit file works fine.

Attached the xdc file.

lmunoz February 06, 2015, 08:21 PM (#9)

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I am sure it is working when you build using ISE, but it isn't working when you build in Vivado. If the host interface was working you would be able to read the CID, even if there is no FMC card present. The clocks from the ADCs might not even be running until the FMC is initialized and you can't do that without the host interface working, so there is no point in putting probes in the FMC part of the code until you can at least read the CID.

The most likely cause of your problem is that the transceivers are not working in Vivado, so your host interface is not working. Xilinx recommends regenerating transceivers in Vivado that came from ISE.

In the UCF file there are these constraints:

# SGMII interface to gigabit phy
NET "SGMII_refclk_p_0" LOC = "AH8";
NET "SGMII_refclk_n_0" LOC = "AH7";
NET "SGMII_refclk_p_0" TNM_NET = "gtrefclk";
TIMESPEC "ts_gtrefclk" = PERIOD "gtrefclk" 8 ns HIGH 50 %;
# SGMII interface to gigabit phy
NET "SGMII_TX_P_0"    LOC = "AN2" ;
NET "SGMII_TX_N_0"    LOC = "AN1" ; #| DIFF_TERM=TRUE;
NET "SGMII_RX_P_0"    LOC = "AM8" ; #| DIFF_TERM=TRUE;
NET "SGMII_RX_N_0"    LOC = "AM7" ; #| DIFF_TERM=TRUE;



Looking through your XDC file I don't see those. How does Vivado know where to put the transceivers?  Look at the built project and see where it placed the transceivers. You might need to add constraints like this

set_property PACKAGE_PIN AH8 [get_ports SGMII_refclk_p_0]
set_property PACKAGE_PIN AH7 [get_ports SGMII_refclk_n_0]

create_clock -period 8 -name gtrefclk [get_ports SGMII_refclk_p_0]

set_property PACKAGE_PIN AN2 [get_ports SGMII_TX_P_0]
set_property PACKAGE_PIN AN1 [get_ports SGMII_TX_N_0]
set_property PACKAGE_PIN AM8 [get_ports SGMII_RX_P_0]
set_property PACKAGE_PIN AM7 [get_ports SGMII_RX_N_0]


If that doesn't work you probably need to LOC the transceivers to the correct location.

# example of a LOC constraint, I'm not sure what the actual location in your design is
set_property LOC GTHE2_CHANNEL_X1Y20 [get_cells sip_sdp_x12_0/gt0_v7_sfpdp_gth_5g0_i/v7_gth_5g0_i/gt0_v7_gth_5g0_i/gthe2_i]
  • « Last Edit: February 06, 2015, 08:28 PM by lmunoz »

leongnrl February 06, 2015, 08:30 PM (#10)

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Originally I had those loc constraint for sgmii ref clk both p and n pins. However after vivado compiled the design, the location constraint of the p pin of the sgmii_refclk is removed by vivado. You can see that vivado does the same thing to sysclk too. Only either one of the p or n pins of the clocks are remained for the differential clocks. I have looked into the schematic of the implemented design and made sure that the package pin are correctly routed to both p and n pins of the clocks.

lmunoz February 09, 2015, 08:34 PM (#11)

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I used the attached constraint file and am I am able to read the CID from the host interface after generating the bit file with Vivado and no other changes.




leongnrl February 09, 2015, 09:10 PM (#12)

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Did you just import the ise project to vivado, or create the vivado from scratch and add sources?

May I ask what version of Vivado are you using? I have just tried to compile with my project with your constraint file but I still can't read the CID from host. I am using 2014.3.1. I also got a timing constraint error with your constraint file from clkout1(period 8ns) to clkout2(period 5ns). They are the generated clock from sysclk.

May I ask what is the release data for your 445_vc707_fmc161 too?
  • « Last Edit: February 09, 2015, 09:18 PM by leongnrl »

leongnrl February 09, 2015, 09:21 PM (#13)

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Is it possible that I can get the vivado proj?

lmunoz February 10, 2015, 01:30 PM (#14)

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I used StellarIP to generate the Vivado project. I use 2014.2. I also get timing errors but don't have any time to fix it now, probably just missing a constraint not really a design problem.


You can get the built project here:
http://4dsp.com/download/vendor/lfmunoz/vc707_fmc161_forum.zip