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fmc161 vivado project

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leongnrl:
I am wonder if there is an vivado project for fmc161. There seems to be a timing/trimming problem when I import the ISE project to vivado.

arnaudNL:
Dear Sir,


Unfortunately not. We only have support for KC705 and VC707 on ISE. Try to look at the "FLATTEN HIERARCHY" option in Vivado it should be set to "NONE".


I believe you can try to send this command in the TCL prompt: set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none


Maybe this will help, otherwise I don't know. You can still try to create a Webcase with xilinx to ask them some pointers.


Best Regards,
Arnaud

leongnrl:
I have tried flatten hierarchy to none but no luck. I am suspecting there is a cross clock domain problem in the code which is ignored in ISE but failed on vivado since vivado deals with timing constraint more strictly.I either got the project compiled but with timing error, or compiled fine with addition clock domain isolation constraint but the fmc161 doesn't run.

arnaudNL:
Dear Sir,


Yes, indeed maybe the timing error is an expected error and a timing ignore is required.


Could you please provide me with the timing report so I can quickly ask a firmware engineer to have a look. I cannot do much but I will give that a try. Anything that could be useful like a detailed error would be a plus.


Best Regards,
Arnaud

leongnrl:
Vivado treats all clock as synchronized to each other unless otherwise specified. At first I got all inter clock timing error between all the clocks. Then, I set all the clocks as asynchronous clock. This get rid of all the timing error but the design doesn't work. To me, it is more like some signals or components are being auto trimmed out but I am not sure what the actual cause it. Can 4dsp look into this problem?

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