I will check with my supervisor regarding to money.
So what I did so far was importing the ISE project 445_vc707_fmc161 to vivado 2014.3. All the sources files are imported to vivado except the constraint file. I create a xdc file with all the pinout out without putting any timing constraint yet. Then I use the constraints wizard, which auto detects the clocks, to enter the timing. Afterward I got lots of inter-clock timing error, so I create another asynchronous clock group timing between adc clocks, mac transceiver clock, and sysclk. After that I got timing error for two of the generated clock from sysclk, so I create a false path between the two.
Got the project compile without timing error, program device, run the fmc161app, couldn't obtain sipcid table error. If I program the device with the bit file that I generated from ISE, everything works.
I put debug core to check adc_phy_i_data but the debug core failed to trigger and seems like there is no clock to the debug core. The clock of adc_phy_i_data is adc_phy_i_clk.
Where should I look at now? Any suggestion will be greatly helpful.