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Simultaneous capture of multiple channels

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philipp:
Hello,

I added chipscope to the VC707 reference design (I added adc0_out_data and adc1_out_data to Chipscope Trigger ports) but then the design has Timing Problems in 156.25 MHz Clock Domain.

I want to check how much phase uncertainty I get when I sample the same signal (Signal Generator connected to a Splitter, connected Channel A + Channel B) on two channels (without using the calibration package).

Do you have a tip or a working design that could help me?

Or, is it possible to sample multiple channels simultaneous with 4FM FMC Analyzer Application?

Best regards,

Philipp

arnaudNL:
Dear Philip,


Both FMC12xApp and the Analyzer are built from the same code base. The firmware is not synchronous on the reference design. Typically in the firmware is a data router and the data router eats any sample flowing from an input (source) not connected to an output (destination).


Our scheme works that way:


- Configure the data router to connect one of the FMC126 channels
- Arm/Trigger
- Save sample to disk, loop to data router configuration for the next channel.


So the samples are not synchronous, they are even completely unrelated. We also don't use chipscope but we are displaying data buffer created by our FMC12xApp software.


What we have is the optional "calibration package for FMC12x". This is a different firmware and software allowing the user to directly use the FMC126 is one channel mode @5Gsps or in two channels mode @2.5Gsps. First of all the firmware is synchronous in the digital domain and then the ADC is calibrated to get a phase, gain and offset sharp on the analogue domain, tuning compensation registers in the e2v chip.


I am attaching its user manual, maybe this is close to what you need to achieve.


Best Regards,
Arnaud

arnaudNL:
Dear Philip,


Can you let me know if the pointers were good enough? Are you able to move forward?


Best Regards,
Arnaud

philipp:
Hello Arnauld,

thank you for your reply.

>The firmware is not synchronous on the reference design.

Well, I don't need synchronous sympling. But just a question: how do you run the sync pin of FMC126? The appropriate code is out-commented in ev10aq190_quad_phy_v7.vhd:614

--sync_out : obufds (Not used on the VC707, signals are mapped to GPIO_LED 6 and 7)
--port map (
--  i  => sync_pls,
--  o  => sync_p,
--  ob => sync_n
--);

>Typically in the firmware is a data router and the data router eats any sample flowing from an input (source) not connected to an output (destination).

But if I connect Chipscope to adc0_out_data, adc1_out_data, adc2_out_data, adc3_out_data in fmc126_if.vhd, the Output is connected.

Best regards,

Philipp

arnaudNL:
Philip,


I am simply telling you sip_routers star are eating input data not connected to an output and this is the first thing we has to do in order to have any coherency between the channels. We added a keep data flag in the FMC126 star, causing data to stay in the internal FIFOs.


The SYNC pulse is done by the CPLD, a software command is sent to CPLD, generating these pulses.


Best Regards,
Arnaud

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