Topic: External clock frequency for FMC230 and VC707  (Read 2896 times)

miroandi January 10, 2015, 03:01 AM

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Hello,


I have a FMC230 and VC707 board.


At the sampling frequency of about 3GHz, DAC and VC707 operated well.


I want to increase the sampling frequency up to 5 GHz.


My questions are


1) The range of external sampling clock input is from 4.5 MHz to 3000 MHz.
( UM023 FMC230 User Manual r1.7 page Is it possible to increase the frequency more than 3 GHz?


2) Xilinx virtex7 (with speed grad -2) in VC707 includes MMCM(PLL), of which input range is 933 MHz.   Is it possible to increase the frequency more than 3 GHz using VC707 ?

3) Any advice to increase the frequency will be very helpful.


Thanks in advance.
Olive



  • « Last Edit: January 12, 2015, 11:05 PM by miroandi »

arnaudNL January 12, 2015, 06:31 AM (#1)

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Dear Sir,


I am reposting your question for a better clarity, someone will answer those.


Quote

I want to increase the sampling frequency up to 5GHz.


My questions are


1) The range of external sampling clock input is from 4.5 MHz to 3000 MHz. ( UM023 FMC230 User Manual r1.7 page 8 ) Is it possible to increase the frequency more than 3 GHz?
2) Xilinx virtex7 (with speed grad -2) in VC707 includes MMCM(PLL), of which input range is 933 MHz. Is it possible to increase the frequency more than 3 GHz using VC707?
3) Any advice to increase the frequency will be very helpful.


Thanks in advance.
Olive.

lmunoz January 12, 2015, 08:17 PM (#2)

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There is no reason to go above DACCLK 2850MHz which is the max allowed according to the DAC data sheet (AD9119_9129).  That would give you 5.7Gsps when using the interpolation.

If you want 5.0Gsps input a 2500 MHz external clock that gets you a 5GHz sampling rate using the interpolation.

Inside the FPGA the clock would be even slower because it is using multiple lanes to send the data. So in the FPGA you don't need a >3Ghz clock, but also it doesn't support that.
 

miroandi January 12, 2015, 11:29 PM (#3)

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Thanks for the fast response.

Best regards,
Olive.
  • « Last Edit: January 13, 2015, 12:41 AM by miroandi »

arnaudNL January 14, 2015, 11:15 AM (#4)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.