Products > FMC Products
FMC168 External Trigger
roengrut:
Hello,
Reply to Ingmar : Thank you very much for recommending enabling the external trigger before arming it. My colleague just tried doing it today.
Reply to Luis : Thanks very much for giving me the hint and showing a result from your test.
Unfortunately, we still get the same outcome as before, receiving the timeout. We also tried to apply the external trigger with arbitrary frequency; e.g. 10 MHz trigger as Luis did. The result is that the output shows "External Trigger : 0.02 MHz" for any frequency we apply, and the same timeout occurs. Is there anything we need to try? Is it related to the BSP of our FMC168 board we are using?
Look forward to receiving your suggestion again. Thank you very much and Merry Christmas to all of you.
Roengrut
lmunoz:
Most likely you are applying a signal that is too weak or the wrong IOSTANDARD. What amplitude and what type of signal are you using? Try increasing the voltage.
roengrut:
Hi Luis,
We apply a single-ended trigger signal through the ssmc connector of the FMC board (Trigger channel). The amplitude is approximately 4 V. The IOSTANDARD is the regular lvds since the signal is converted to it on board and we do not modified the VHDL part of the hardware design. If there is anything we should do, please suggest us again. Thank you very much.
Roengrut
iklink:
Dear Roengrut,
4V amplitude could potentially damage the device because it is LVTTL compatible and has got a maximum input voltage of +3.3V. Are you using a DC-coupled signal source? The trigger signal must have a logic low level of 0V < signal < 0.5V and a high level of 1.25 < signal < 3.3V. Also, the trigger input has got a weak pull-down to ground, so it's not possible to use an AC-coupled signal.
I double checked the test report of your FMC and at the time of manufacturing testing the trigger seemed to work. Which carrier board are you using? One of the Xilinx development boards? Would it be worthwhile to double check your synthesis and implementation output to see that the trigger inputs of the FPGA properly connect to the correct logic?
Best regards,
Ingmar
ebarhorst:
Dear Roengrut,
would you have an update for us on this topic?
Best regards,
Erik
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