Topic: FMC12xAPP.exe / Configuring FMC12x / PLL Not Locked !  (Read 10380 times)

didier jehanno December 04, 2014, 01:21 PM

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Dear 4DSP Support staff,

FMC126 S/N "REGE002065" installed on VC707 slot HPC#1.
No signal is connected to the FMC126.
E2V ADC is cooled with > 500 LFM heatsink + fan, see attached doc.pdf.
I have added a PT100 sensor on the ADC and temp. readout value is consistent with 7411 IC values.

my computer is a Windows 7 machine with ISE 14.7 + StellarIP 1.2.3.0.

I am using 4FM Getting Started Guide r4.15.
At chapter 11 "Evaluating FMC AD/DA product using Xilinx Dev. Kits", step 10.

I launch : FMC12xAPP.exe 1 VC707 0 0 4
I get an error "PLL Not Locked".

I have checked /FMC Board Support Package/Refs/Software/FMC12x/main.cpp.
i2cmaster_getdiagnosticsFMC12x() line 758 successfuly prints the diagnostic, return values seem consistent.
but then FMC12x_init() line 801 outputs the error -2 (FMC12X_CLOCKTREE_ERR_CLK0_PLL_NOT_LOCKED).
Please look "doc.pdf".

[2014.12.06] I have updated the doc.pdf with VS2012 debug infos in step mode.
Line 263 of fmc12x_clocktree.cpp : // verify CLK0 PLL status
Line 264 sipif_readsipreg is called with addr = 0x3502 + offset 0x1F
sipif_readsipreg calls g_pETH_ReadSystemRegister with same addr, and this function return 0x78.
0x78 is stored in dword variable.
Bit 0 SHOULD BE 1, but it's 0 =>>> "PLL not locked!!!\n"
It leads to the error -2 :
#define FMC12X_CLOCKTREE_ERR_CLK0_PLL_NOT_LOCKED   -2 /*!< The PLL in the clock tree chip did not lock after a reset */


I did not find a post related to this error, sorry. A Search tool could be convenient.

I would have few questions please :

[Q1] do you confirm that the main.cpp works only with FMC126 daughter board on HPC#1.
[Q2] for option "4"  (Internal VCO option -C60) what does -C60 stand for ?
[Q3] any idea about the PLL not locked error ? I would like to work with internal PLL first (I don't have a 2.5GHz clock synthetiser yet)
[Q4] there is a "CNRS" forum, shall I use it as my lab is part of IN2P3 Institute, itself part of CNRS ?

[Q5] is there a search tool in the forum ?
Sorry, I eventually found the answer here :
Topic: Why no "search" function in the forums?  (Read 750 times).
Search function is limited to admin/moderators.
Question solved.



Many thanks for your help.

didier

didier jehanno
CNRS/LAL Orsay
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  • « Last Edit: December 06, 2014, 08:13 AM by didier jehanno »

arnaudNL December 09, 2014, 12:06 PM (#1)

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Bonjour Didier,


Sorry for reacting late on your post, I failed to receive the notification, my apologies for that. So the C60 bit is the custom ordering option C60 and this is about modifying the FMC12x hardware so the internal VCO (in the clocktree chip) can be used. The software will only operate fine with such a modified hardware, this can explain why the PLL does not lock.


I believe you should use 0 for 2.5GHz standard VCXO on the board. And clock mode should be 0 for internal or 1 for external clock. The latest one forces you to use a 2.5GHz clock on the external clock input and run the board without to change the software.


I hope that helps,
Arnaud

didier jehanno December 09, 2014, 01:06 PM (#2)

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Bonsoir Arnaud,

Merci bcp pour la réponse. ça fonctionne, voir-ci-dessous. Il reste Q1 et Q4 svp.

[Q1] do you confirm that the main.cpp works only with FMC126 daughter board on HPC#1.

Could you please answer ?
In my design, I MUST use FMC126 on slot #2 because there is a FMC204 on slot #1.
If I do the opposite, I will just have 2 ADC channels instead of 3.

[Q2] for option "4"  (Internal VCO option -C60) what does -C60 stand for ?

OK, understood.
I don't have requested this C60 option (if not mistaken, I did not know it was even existing).


[Q3] any idea about the PLL not locked error ? I would like to work with internal PLL first (I don't have a 2.5GHz clock synthetiser yet)


Problem solved. I already tried option 0 but the program was pending. This time I tried 4 times and it works !
With option 4, it works on first attempt.

So the PLL is now locked. I have plotted the data. Please see doc2. I will also plot histogram later.


[Q4] there is a "CNRS" forum, shall I use it as my lab is part of IN2P3 Institute, itself part of CNRS ?

Could you please answer ?


So, I would just need answers for Q1 and Q4, then ticket can be closed I think.

a+.
didier
didier jehanno
CNRS/LAL Orsay
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arnaudNL December 10, 2014, 10:46 AM (#3)

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Dear Didier,


[Q1]


That depends on the carrier. On the VC707, StellarIP should be able to either tied the logic on HPC1 or HPC2. Open the 244_ .dsn in StellarIP, accept the next message box and then double click on sip_fmc126. There you will see an "Index" field set to 0. Changing that to 1 will make StellarIP to create a firmware for HPC2 when you press Generate. You can check both (index=0 and index=1) UCF output they will be slightly different.


As far as FMC204 on VC707 is concerned, only HPC1 is supported so the "Index" field wont work here.


That should work out just fine. But I must admit we haven't tried this FMC126/FMC204 combo. The FMC170 seems like a good alternative to this combo


[Q4]


That's fine indeed. If you desire a dedicated forum for your lab instead I can arrange that, let me know.


Best Regards,
Arnaud

didier jehanno December 11, 2014, 04:50 AM (#4)

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dear Arnaud,

Thanks for the last details.


[Q1] That depends on the carrier. On the VC707, StellarIP should be able to either tied the logic on HPC1 or HPC2. Open the 244_ .dsn in StellarIP, accept the next message box and then double click on sip_fmc126. There you will see an "Index" field set to 0. Changing that to 1 will make StellarIP to create a firmware for HPC2 when you press Generate. You can check both (index=0 and index=1) UCF output they will be slightly different.

OK, thanks for the details. I will generate new bitstream for my config and test it.

As far as FMC204 on VC707 is concerned, only HPC1 is supported so the "Index" field wont work here.

I see. In my design, FMC204 will be located on HPC1, so it's consistent with 4DSP specs.

That should work out just fine. But I must admit we haven't tried this FMC126/FMC204 combo. The FMC170 seems like a good alternative to this combo.

I intend to :

1- generate .bit for FMC126 on HPC2 (index = 1). Then test,  with HPC1 empty.
2- test FMC204 on HPC1, with HPC2 empty, using 4DSP available .bit
3- developing a StellarIP model with both FM216 + FMC204 and test it.


[Q4] That's fine indeed. If you desire a dedicated forum for your lab instead I can arrange that, let me know.

I could use the existing CNRS forum. Do you agree ?
It would prevent from creating a new forum only for my lab.
Or you could create a "sub-forum" Inside CNRS forum...

but yes, I would rather prefer to be located in a dedicated area, if possible and allowed.


Regards.
didier


Best Regards,
Arnaud
didier jehanno
CNRS/LAL Orsay
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arnaudNL December 11, 2014, 07:58 AM (#5)

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Bonjour Didier,


So, I created a specific group for your lab and you are the only one (besides 4DSP) having access to it.


You will not see the CNRS group anymore. We have three CNRS entities, "CNRS" with some people from a univeristy in Paris another one is CNRS OBS NANCAY. The latest one is the famous station de radioastronomie I would say.


If a day we need to merge the groups we can do that.


Best Regards,
Arnaud
 

arnaudNL December 12, 2014, 11:20 AM (#6)

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Didier,


I assume I can close this specific topic? Everything was answered I believe?


Best Regards,
Arnaud

didier jehanno December 15, 2014, 05:50 AM (#7)

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Hello,

[Q] I assume I can close this specific topic? Everything was answered I believe?

yes, it's fine, this topic should be closed.

I will just open a new ticket for FMC170 board (quite new for me, so I have few questions) in the CNRS IN2P3 forum.

didier


didier jehanno
CNRS/LAL Orsay
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arnaudNL December 15, 2014, 06:16 AM (#8)

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Perfect Didier!


Best Regards,
Arnaud

arnaudNL December 15, 2014, 06:16 AM (#9)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.