Dear lmunoz,
Thank you for your information.
As for the vhd files for DAC clock, data, and frame, I used the Xilinx component "OSERDES".
(the clock was input to an MMCM, converted to the single-ended scheme, and input to those OSERDES.)
Besides, I also tried self-made OSERDES.
The timing shift occurs for both of the above cases.
The time resolution of the timing shift is around 2 ns, and its dynamic range is around 150 ns.