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Timing shift of FMC DAC output

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fmcuser:
Hello,
I am using a development board ML605 with an FMC150 connected to the LPC site. I want to generate two signals, one is output from a DAC of FMC150, the other is output from a GPIO SMA of ML605. These two signals are supposed to begin at the same time, same phase. However, only the initiation timing of the waveform from the DAC of the FMC150 shifts. This shift occurs every time I power on, re-program or does a reset through a push button written in the program, all using the same .bit file.

Can anybody help me solve this problem?
Thanks in advance

arnaudNL:
Dear Sir,


You need to get the design synchronous. This is outside the scope of technical support but I assume you want to use your DAC clock as reference to your SMA clock so it is always in phase?


Not sure, just an idea.


I hope that helps,
Arnaud

fmcuser:
Dear Arnaud,

Thank you for your advice.

The 491.52-MHz clock on FMC150 is the main clock source in my design. CDCE72010 outputs 61.44-MHz clock from U4P/N (to FPGA) and U7P/N (to DACs). I used the 61.44-MHz clock coming from U4P/N as reference to my SMA signal (ML605) and the signal which is designed to be output from a DAC (FMC150). Therefore, both have to be always in phase.

However, they are not working as intended. Only the initiation timing of the signal from the DAC shifts every time I power on, re-program or does a reset through a push button written in the program, all using the same .bit file.

I would appreciate it if you would give me any suggestion.

lmunoz:
Hi,

If I understand correctly you want to align a clock out of the SMA connector to a signal coming out of the DAC?

Have you completely changed the reference design provided? What signal are you sending out the DAC and how are you generating it, are you using the 4dsp waveform repeat code? When do you start sending it? What clock are you using on the SERDES the same one going to the SMA connector?


-Luis

fmcuser:
Dear Luis,


Thank you for your reply.

Yes, I want to align a clock out of the SMA connector to a signal coming out of the DAC. I am not using the reference design. Both of those two signals are identical 4-MHz clock. I am not using the 4DSP waveform repeat code.

We had tested our design, and we did not find any suspicious areas that will create that shift. The DAC data bits are in sync with the yellow trigger in our design. The clock that I am using for SERDES is the one coming from U4P/N, which is 61.44 MHz.

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