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Understanding Fmc15xAPP

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arnaudNL:
Hello Joao,


I am not able to really go in depth in such inquiries. According the elements in your email, the ADC is sampling at 250Msps.


The DAC have a waveform memory. This goes against what you try to achieve I believe, once again thinking out of the box, you want to have the DAC playing one sample each time a sample is pushed to its input wormhole. The DAC have interpolation settings to look at and so on. But this is what I mean by streaming, you want to remove the waveform memory from the DAC side and then connect both wormholes (input and output) with it other.


There might be format difference in the output data (coming from the A/D) and the input data (expected from the D/A) you need to compensate from.


It is surely a fun design to implement. You could place a "DSP" star on the path, a custom star you create doing a 180 degree phase inversion.


I hope this extra information helps you out. Always feel free to ask, we are always glad to help our customer when we can!


Best Regards,
Arnaud

JoaoFerreira:
First of all, thanks again for the help.


I know that you are doing something you don't need to do, but i think i'm not understanding correctly and i'm confused. Correct me if 'im wrong please, so what you are saying is that i need to change the VHD file (sip_fmc150) in order to remove the waveform memory from DAC, and to conect DAC output to ADC input or i just need to change the stellar ip design? Probably both things.


Sorry again about the confusion


 

arnaudNL:
Dear Joao,


This is what I expect yes. You would need to change FMC150 star vhdl code to bypass the waveform memory in the source fmc150 star code in your library and modify your stellarIP schematic to connect input ports to output ports.


You can also decide to only focus on modifying the ISE project created by StellarIP; Modify FMC150 code as well as the top level.


I hope that helps!


Best Regards,
Arnaud

arnaudNL:
Dear Joao,


Was this information sufficient, can I close this topic?


Best Regards,
Arnaud

JoaoFerreira:

--- Quote from: arnaudNL on December 02, 2014, 05:18 AM ---
You can also decide to only focus on modifying the ISE project created by StellarIP; Modify FMC150 code as well as the top level.


--- End quote ---


I understand almost everything you said, the only thing that i have doubt is what i quoted above. Correct me if i'm wrong, what you said is that i can generate the ISE project and try to modify it to do what i want, but i need to modify the FMC 150  VHDL code as well?


After some brainstorming, i came to an hypothesis, so since i need to change sip_fmc150 vhdl file to make it connect ADC0 to DAC0, i thought well if i just want to do that and while doing that recording some samples, in a txt file for example, i just need a similar stellar ip star for FMC 150, but without DAC0 and DAC1 wormhole in and ADC1 out wormhole, and insert a DAC0 wormhole out.


So basically i do that out wormholes to process the samples and recording them to a txt file with the help of zedboard connection. And i just have to connect in FMCxAPP the ADC with DAC to make the internal operation of do a bypass from data of ADC to DAC.


In other hand, i'm thinking that this internal bypass is probably needed to program in stellar IP. But that seems strange because i just need to connect the ADC0 wormhole out to DAC0 wormhole in, and i can do this in the reference design given. Of course then in the FMCxAPP how should i input data in ADC? I assume that if i put a sinewave in the ADC input port of FMC150 it is already acquiring data? And  probably doing this bypass means that i'll connect ADC to DAC directly and assuming that ADC is acquiring data, it is transmiting data to DAC at the same time.

Thanks for all the help and patience.


Best regards,


Joao

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