Topic: FMC125 Sample rate change  (Read 6832 times)

rakeshmg November 08, 2014, 04:36 PM

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Hello,


I would like to change the same rate on the FMC125 card to around 250MHz. Is this possible? I have tried looking at the datasheets for the EV8AQ and the clock generator, but I do not find any such setting.


The problem is that I need 16k samples of data sampled at around 250MHz. Since by default the ADC is working at 1.25GHz, and can pull a maximum of 64k samples sampled at 1.25Ghz.
If i throw away one fourth of the samples to "reduce" the effective same rate to around 312.5MHz, i would end up with 4k samples per data pull.


Since I need 16k samples, I would have to do a pull 4 times, which causes data inconsistency between my 16k samples at 4k, 8k and 12k region.


It would be much nicer, if i could pull 16k continuous samples from the ADC, which are sampled at a lower rate. How can I do this?


Regards,
RAkesh

arnaudNL November 10, 2014, 08:55 AM (#1)

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Rakesh,


It is a reference design, if you need more than 64kB storage, create a star having more than that. In order to sample at different frequencies you need to modify the clock tree chip configuration, you can only divide the fVcxo / n (1250, 625, 416.66, 312.5, etc...).


Modifying the reference design for all the possible use is not covered by standard technical support so I cannot explain everything to the details. If you need such a service from us you can purchase engineering/integration support contracts and then you will have our engineers helping you out in the details.


Best Regards,
Arnaud

arnaudNL November 17, 2014, 09:21 AM (#2)

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Dear Rakesh,


Long time I haven't heard from you, are you able to move forward, can I close this topic?


Best Regards,
Arnaud

rakeshmg November 17, 2014, 11:16 AM (#3)

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Hello Arnaud,


Thank you for your reply.


I have tried changing the pre-scaler on the VCO which is the one you suggested, but the ADC phy clocks that are measured did not really change.


I gave up and have resorted to dropping 3/4 of the samples i get from the ADC to artificially reduce the sampling rate to 1.25e9/4..


Thanks,


Rakesh

arnaudNL November 19, 2014, 06:17 PM (#4)

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This topic is being closed because the issue is considered as resolved by 4DSP. Feel free to create a new topic for any further inquiries.