Luis,
Thanks for clarification.
I have few more questions related to reference design:
- Are dac_clock and dac_data outputs programmed to change simultaneously, i.e. with zero setup time? That's how code looks to me.
- looking at dac3283 datasheet, the minimal setup time is NEGATIVE 25 ps. Do I understand it correct that dac_data can be settling for up to 25 AFTER dac_clock transition, which would clarify the above question I have as well?
- Ref. design is set to output dac_data at 122.88 MSPS, while reading ADC data at twice that rate. Are there any particular technical limitations in the hardware or reference firmware I should be aware of if I am to double the dac_data sample rate to match ADC rate?